Sanyo VPC-S5, Руководство по обслуживанию

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3. Part of IC906 (H Driver) and IC901 (V Driver)
An H driver (part of IC906) and V driver (IC901) are neces-
sary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC906 has the generation of horizontal transfer clock and the
function of H driver, and is an inverter IC which drives the
horizontal CCDs (H1 and H2). In addition the XV1-XV6 sig-
nals which are output from IC101 are the vertical transfer
clocks, and the XSG signal which is output from IC101 is su-
perimposed onto XV1, XV3 and XV5 at IC901 in order to gen-
erate a ternary pulse. In addition, the XSUB signal which is
output from IC101 is used as the sweep pulse for the elec-
tronic shutter, and the RG signal which is output from IC906
is the reset gate clock.
Fig. 1-4. IC906 Block Diagram
4. IC906 (H Driver, CDS, AGC and A/D converter)
IC906 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
HØ1 (A and B) and HØ2 (A and B) are generated inside, and
output to CCD.
The video signal which is output from the CCD is input to pins
(27) of IC906. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier). It
is A/D converted internally into a 10-bit signal, and is then
input to ASIC (IC101). The gain of the VGA amplifier is con-
trolled by pin (31)-(33) serial signal which is output from ASIC
(IC101).
CCDIN
RG
H1-H4
VD HD SDATA SCK
SL
CLI
DOUT
VRB
VRT
PRECISION
TIMING
CORE
SYNC
GENERATOR
PxGA
VGA
ADC
10
2~36 dB
VREF
CLAMP
INTERNAL
REGISTERS
INTERNAL
CLOCKS
CDS
CLAMP
HORIZONTAL
DRIVERS
4
Fig. 1-3. IC901 Block Diagram
20
21
22
23
24
25
27
28
1
2
3
9
10
11
12
13
14
15
16
6
18
17
7
IV1
CH1
IV3
CH2
CH3
IV2
IV6
IV5
CH4
CH5
ISUB
OV6
OV8
OV7
OV4
OV5
OV3
OV2
OV1
VL
VL
VM
VM
Level
conversion
26 IV4
8 OSUB
19
VDC
VDC
VL
VHH
Level
conversion
Level
conversion
Level
conversion
VL
VL
VH
VL
VH
VDC
VDC
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VL
VH
VDC
Level
conversion
VH
VDC
VHH
VL
2-level
VL
VM
VH
VL
VM
VH
VL
VM
VL
VM
VH
VL
VM
VH
VL
VM
VL
VM
VH
VL
VM
2-level
3-level
3-level
2-level
3-level
3-level
2-level
4
VH
5
VHH
VL
3-level
5. Lens drive block
5-1. Shutter drive
The shutter drive signal (SIN1 and SIN2) which is output from
the ASIC is drived the shutter constant level driver (IC951),
and then shutter plunger is opened and closed.
5-2. Iris drive
The iris stepping motor drive signals (IIN1 and IIN2) which are
output from the ASIC (IC101) are used to drive by the motor
driver (IC951).
5-3. Focus drive
The focus stepping motor drive signals (FIN1, FIN2, FIN3 and
FIN4) which are output from the ASIC (IC101) are used to
drive by the motor driver (IC951). Detection of the standard
focusing positions is carried out by means of the
photointerruptor (FPI-E) inside the lens block.
5-4. Zoom drive
The zoom DC motor drive signals (ZIN1 and ZIN2) which are
output from the ASIC (IC101) are used to drive by the motor
driver (IC951). Detection of the zoom positions is carried out
by means of photoreflector (ZPI-E) inside the lens block.