Sanyo VAR-G6E, Руководство по обслуживанию

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Table 1-1. CCD Pin Description
Fig. 1-1. CCD Block Diagram
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CA1 and A PART OF CA2 CIRCUIT
DESCRIPTIONS
Around CCD block
1. IC Configuration
CA1 board
IC901 (ICX274AQ) CCD imager
CA2 board
IC901 (H driver, CDS, AGC and A/D converter)
2. IC901 (CA1) (CCD imager)
[Structure]
Interline type CCD image sensor
Image size Diagonal 8.293 mm (1/1.8 type)
Pixels in total 1688 (H) x 1248 (V)
Recording pixels 1600 (H) x 1200 (V)
Pin No.
1
Symbol
2
3
4
5
6
7
8
9
10
Vø
4
Vø
3A
Vø
3B
Vø
3C
Vø
2A
Vø
2B
Vø
2C
GND
V
OUT
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Signal output
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Vø
1
Vertical register transfer clock
Pin No.
11
Symbol
12
13
14
15
16
17
18
19
20
V
DD
øRG
Hø
2B
Hø
1B
GND
øSUB
C
SUB
Hø
1A
Hø
2A
Pin Description
Circuit power
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
Substrate clock
Substrate bias
Horizontal register transfer clock
V
L
Protection transistor bias
3. IC904 (V Driver) and IC901 (CA2 board) (H driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD.
IC904 are V driver. In addition the XV1-XV4 signals which are
output from IC102 are the vertical transfer clocks, and the
XSG signal which is output from IC102 is superimposed onto
XV2 and XV3 at IC902 in order to generate a ternary pulse.
In addition, the XSUB signal which is output from IC102 is
used as the sweep pulse for the electronic shutter. A H driver
is inside IC901 (CA2 board), and H1A, H1B, H2A, H2B and
RG clock are generated at IC901 (CA2 board).
4. IC901 (CA2 board)
(CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(29) of IC901 (CA2 board). There are inside the sampling hold
block, AGC block and A/D converter block.
The setting of sampling phase and AGC amplifier is carried
out by serial data at Pin (37) of IC911. The video signal is
carried out A/D converter, and is output by 10-bit.
8
1
18 19 20
2 3 4 5 6 7
13 14 15 16 17
G
B
R
G
R
G
B
G
B
G
B
G
R
G
R
G
B
V
DD
GND
C
SUB
V
L
R G R
G
9
10
12
11
GND
V
OUT
G B G
R G R
G B G
B
G
(Note)
Vertical register
Horizontal register
(Note) : Photo sensor
Fig. 1-2. IC901 Block Diagram
CCDIN
RG
H1-H4
VD HD SDATA SCK
SL
CLI
CLPOB
CLPDM
DOUT
VRB VRT
PRECISION
TIMING
CORE
SYNC
GENERATOR
PxGA VGA ADC
12
2~36 dB
PBLK
VREF
CLAMP
INTERNAL
REGISTERS
INTERNAL
CLOCKS
CDS
CLAMP
HORIZONTAL
DRIVERS
4