-94-
IIC Bus D/A Converter (M62393FP Fan Control, IC7971)
Control Port Functions
Pin No. Function Name
Function
Pol.
Action
Stand-by
Power On
1
Reset Input
I
→
2
IIC BUS SCL
I
→
3
IIC BUS SDA
I/O
→
4
FAN_CONT5
FAN_FN905 Control Voltage (Lamp1&2 Top)
AO
→
0:FAN Max ~ 255:FAN Min
5
FAN_CONT6
FAN_FN906 Control Voltage (Panel Cooling Fan R)
AO
→
0:FAN Max ~ 255:FAN Min
6
FAN_CONT7
FAN_FN907 Control Voltage (Panel Cooling Fan G)
AO
→
0:FAN Max ~ 255:FAN Min
7
FAN_CONT8
FAN_FN906 Control Voltage (Panel Cooling Fan B)
AO
→
0:FAN Max ~ 255:FAN Min
8
GND
-
→
9
DAC Upper Ref. Voltage(CH5~CH8)
-
→
10
GND
-
→
11
DAC Upper Ref. Voltage (CH1~CH4)
-
→
12
FAN_CONT1
FAN_FN901 Control Voltage (Lamp1 Cooling Fan)
AO
→
0:FAN Max ~ 255:FAN Min
13
FAN_CONT2
FAN_FN902 Control Voltage (Power Cooling Fan)
AO
→
0:FAN Max ~ 255:FAN Min
14
FAN_CONT3
FAN_FN903 Control Voltage (Lamp2 Cooling Fan)
AO
→
0:FAN Max ~ 255:FAN Min
15
FAN_CONT4
FAN_FN904 Control Voltage (Lamp1&2 Bottom)
AO
→
0:FAN Max ~ 255:FAN Min
16
Power for Output Buffer (4.5V ~ 5.5V)
-
→
17
Power 5V±10%
-
→
18
Slave Address Setting Pin2 (Vdd)
I
→
H
19
Slave Address Setting Pin1 (GND)
I
→
H
20
Slave Address Setting Pin0 (GND)
I
→
H
PIN
PORT SIGNAL
FUNCTION
I/O
NOTE
3
A3
FAN_MTR7
Fan Motor Speed Input FN907
I
4
A4
FAN_MTR4
Fan Motor Speed Input FN904
I
62
B3
FAN_MTR8
Fan Motor Speed Input FN908
I
63
B4
FAN_MTR5
Fan Motor Speed Input FN905
I
71
B12
FAN_MTR1
Fan Motor Speed Input FN901
I
74
B15
IN0HS
FPGA H-Sync. Output
O
114
C4
FAN_MTR6
Fan Motor Speed Input FN906
I
75
C15
IN0CLK
FPGA Clock
O
18
C16
IN0VS
FPGA V-Sync. Output
O
158
D5
FAN_MTR3
Fan Motor Speed Input FN903
I
159
D6
FAN_MTR2
Fan Motor Speed Input FN902
I
76
D15
SCL0_S3.3V
IIC Bus Clock
I
19
D16
SDA0_S3.3V
IIC Bus Data
I/O
194
E6
P-FAIL_1.0V
Power Failure Detection Input 1.0V
I
222
F7
P-FAIL_S1.8V_KS
Power Failure Detection Input S1.8V on Keystone
I
245
H10
P-FAIL_S2.5V_KS
Power Failure Detection Input S2.5V on Keystone
I
228
H11
P-FAIL_S3.3V
Power Failure Detection Input S3.3V
I
251
J7
P-FAIL_S5V
Power Failure Detection Input S5V
I
204
J12
SW_PF3.3V
Power Fail Switch 3.3V
O
216
K5
P-FAIL_S-5V
Power Failure Detection Input S-5V
I
237
K6
P-FAIL_PJ
Power Failure Detection Input Network
I
245
L5
P-FAIL_15V
Power Failure Detection Input 15V
I
236
L6
P-FAIL_RLY
Power Failure Detection Input Relay circuit
I
183
N5
SHUTTER_POSI1
Shutter Position Detection Input 1
I
182
K6
SHUTTER_POSI2
Shutter Position Detection Input 2
I
144
P5
Shutter Motor Drive +
O
97
R5
SHUTTER-
Shutter Motor Drive -
O
88
R14
SCLK_FRT
Bus Clock
O
42
T5
VS_ADFRT
V-Sync. Input AD
I
41
T6
HS_ADFRT
H-Sync. Input AD
I
38
T9
CLK_ADFRT
Clock AD
I
33
T14
SDAT_FRT
Bus Data
I/O
FPGA (XC3S50A, IC5201)
PIN
PORT
SIGNAL
FUNCTION
I/O
NOTE
97
P15
W_RC_SW
Wired Remote Control Detect Input
I
98
P16
LAMP-ID_INH1
Lamp-ID Drive Input
I
99
P17
INT_FRT
SW FPGA Config
O
100
P18
DONE_FRT
SW FPGA Config
O
Содержание PLC-XTC50L
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