Sanyo DVD-SL33KR, Руководство по обслуживанию

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ZD
501
3.
6V
C5
0
7
100U
F
/16V
C5
0
8
104
C5
0
6
4.
7U
F
/50V
R5
0
7
10K
TA
2
0
6
PL
A
Y
TA
2
0
2
F.
S
H
IP
D
501
1N
4148
D5
0
2
1N
4148
R5
0
8
10K
1
2
3
SN
501
R
E
M
O
T
E
38K
H
z
C5
0
3
100U
F
/10V
C5
0
2
104
TA
2
0
3
PO
W
E
R
/S
T
B
TA
2
0
1
B.SHI
P
TA
2
0
5
OP
EN/
C
LOSE
R5
0
2
10 O
H
M
R504 22K
C
501
221
F1
1
F1
2
P16
4
P15
5
P14
6
P13
7
P12
8
P11
9
P10
10
P9
11
P8
12
P7
13
P6
14
P5
15
P4
16
P3
17
P2
18
P1
19
NX
20
NX
21
NX
22
NX
23
NX
24
1G
25
2G
26
3G
27
4G
28
5G
29
NP
30
F2
31
F2
32
NX
3
VF
D
501
HNV
-0
5
S
S4
8
PC
O
N
DGND VFD
C
E
VFD
C
L
K
VF
D
-DA
IR AG
N
D
v+ v-
1 2 3 4 5 6 7 8 9
10 11 12 13 14
CN
5
0
1
CON1
4
R5
0
9
10K
+5
V
C5
0
9
104
DC
-22V
TA
2
0
4
STOP
R
515
27K
(51K
)
SW
1
1
IR
_IN
2
SDA
3
SCL
4
DO
5
DI
6
VS
S
7
CLK
8
STB
9
K1
10
K2
11
K3
12
K4
13
VDD
14
S1/KS1
15
S2/KS2
16
S3/KS3
17
S4/KS4
18
S5/KS5
19
S6/KS6
20
S7
21
S8
22
S9
23
S1
0
24
S1
1
25
S1
2
/G
1
1
26
VE
E
27
S1
3
/G
1
0
28
S1
4
/G
9
29
S1
5
/G
8
30
S1
6
/G
7
31
G6
32
G5
33
G4
34
G3
35
G2
36
G1
37
VDD
38
PW CTL
39
LED3
40
LED2
41
LED1
42
VSS
43
OSC
44
IC
501
TP6317
R5
1
7
10 O
H
M
R5
1
9
0
R5
2
0
0
R5
2
2
0
R5
2
6
33
SDA SCL
R
527
100K
+D
5
V
R5
2
8
4.
7k
Q5
0
2
2S
C
1623
R5
3
0
1K
R5
3
1
1K
Q
501
2S
C
1623
R
532
100K
ASSE
MBL
Y
NOT
E
:
1. XE
/J
P VE
R USE
6317IC,
DE
L
E
T
E
R
5
06
2. C
A
/US/SS/AU VE
R
. USE
6312FIC. 3
. U
S
E 6312F
,
DEL
ETE
R530,R531,R522,R519,R520,R517,R501, Q502. 4. R515 IC6312F USE
51K
OHM,
IC6317 USE
27K
OHM.
R
501
4.
7K
R5
0
6
4
.7K
TP
6312F
R
505
OP
EN
R5
0
3
0
O
H
M
SCHEMATIC DIAGRAM (CONTROL)
This is a basic schematic diagram.
Assembly
Note:
If
using
SST
family
Flash,
not
install
R138;
If
using
Intel
family
Flash,
n
ot
install
R137.
During
Work
and
D
ownload
mode,
s
hort
pin2
and
p
in3
o
f
C
N104
and
CN105;
During
Debug
mode,
s
hort
p
in1
a
nd
pin2
of
CN104
and
C
N105.
If
use
+3.3v
,not
install
R
134
If
use
+5v
,not
install
R133
During
w
ork
install
R160/R161
0
R
MEMRD# RESET# MEMW
R
#
MEMDA[0..15]
FLASHCS#
MEMAD[0..19]
SSTAD19
IntelAD19
SSTAD19
MEMD
A
5
MEMDA
1
2
MEMDA
1
5
MEMDA
1
0
MEMDA
1
1
MEMD
A
0
MEMD
A
3
MEMD
A
1
MEMD
A
2
MEMDA
1
4
MEMD
A
4
MEMD
A
9
MEMD
A
7
MEMD
A
8
MEMDA
1
3
MEMD
A
6
MEMCS
1
#
RAMCS#
MEMCS
0
#
MEMW
R
#
MEMRD#
MEMDA
1
3
MEMAD
1
5
RAMCS#
GND
MEMAD
1
3
GND
MEMD
A
2
MEMW
R
#
MEMA
D
7
MEMAD
1
1
MEMD
A
9
MEMDA
1
1
MEMA
D
5
MEMDA
1
5
MEMA
D
4
MEMD
A
1
MEMAD
1
4
MEMAD
1
6
MEMRD#
MEMA
D
8
MEMA
D
2
MEMD
A
4
MEMDA
1
4
MEMD
A
5
MEMD
A
3
MEMAD
1
2
MEMAD
1
8
MEMD
A
7
MEMAD
1
0
MEMDA
1
2
MEMA
D
1
MEMD
A
0
MEMD
A
6
MEMD
A
8
MEMDA
1
0
MEMA
D
0
MEMA
D
9
MEMA
D
6
MEMW
R
#
MEMAD
1
7
MEMA
D
3
SD3
FLASHCS#
VCC_MEM
VCC_MEM
VCC_MEM
VCC_MEM
MEMA
D
5
MEMAD
1
8
MEMA
D
2
MEMA
D
4
MEMAD
1
1
MEMAD
1
9
MEMA
D
0
MEMAD
1
6
MEMAD
1
7
MEMAD
1
4
MEMA
D
3
IntelAD19
MEMA
D
9
MEMA
D
7
MEMA
D
6
MEMAD
1
0
MEMAD
1
3
MEMA
D
1
MEMAD
1
2
MEMAD
1
5
MEMA
D
8
+3.3V
+5V-
S
T
B
SD3
SD3
VCC
VCC
+3.3V
+5V-
S
T
B
R132 4.7k
C147 0.1uF
R137
0R/NC
U104 SST39VF800/TSOP
18 19 20 21 22 23 24 25
27 29 37 44
48
1 2 3 4 5 6 7 8
31 33 35 38 40 42
17
46 30 32 34 36 39 41 43 45 15
47 26 28 11 12 16
9
13 14
A7 A6 A5 A4 A3 A2 A1 A0
GND
DQ0
VCC
DQ7
A16 A15 A14 A13 A12 A11 A10 A9 A8
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6
A17
GND
DQ8 DQ9
DQ10 DQ11 DQ12 DQ13 DQ14
DQ15/A-1
RY/BY
BYTE CE OE WE RST A18 A19
I-Vpp
I-WP#
R136 1K
C148
0.1uF
CN103
DEBUG SRAM I/F
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 42 40
41
R133
0R/NC
R161
NM/0R
R160
NM/0R
R138
0R/NC
R135
1K
CN104 3 PINS HEADER 1 2 3
R134
0
R/NC
U105 AT24C02N-10SI-2.7
1 2 3 4
5 6 7 8
A0 A1 A2
GND
SDA SCL WP VCC
CN105 3 PINS HEADER 1 2 3
GND
MEMDA[0..15] MEMAD[0..19]
SDA
SCL
+3.3V
RESET#
MEMCS
0
#
MEMCS
1
#
RD- WR-
SD3
VCC +5V-
S
T
B
This is a basic schematic diagram.
SCHEMATIC DIAGRAM (MEMORY)