Sanyo DC-DA3300M, Руководство по обслуживанию

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IC BLOCK DIAGRAM & DESCRIPTION
IC103 M12L16161A-7TG (Synchronous DRAM)
CLK
CLK
ADD
LCKE
CS RAS CAS WE L(U)DQM
LDQM
LWCBR
CKE
LCAS LWE LCBR
LCBR
LRAS
LRAS
DQi
LDQM
LWE
Bank select Data Input Register
I/O Control
O
utput Buff
er
Sense AMP
Ro
w Decoder
Ro
w Buff
er
Refresh Counter
Col.
Buff
er
Address Register
512K
X
16
512K
X
16
Column Decoder
Latency & Burst Length
Programming Register
Timing Register
1
2
3
4
5
6
7
8
9
10
11
12
1
3
1 4
15
16
17
1
8
1 9
20
21
22
2
3
2
4
25
50
49
48
4 7
4
6
4
5
44
43
4 2
4
1
4 0
39
38
3 7
3
6
3 5
34
33
3 2
3
1
3 0
2
9
2 8
27
26
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ
3
V
DDQ
DQ
4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A
3
V
DD
V
SS
DQ15
DQ1
4
V
SSQ
DQ1
3
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ 9
DQ5
V
DDQ
N .C/R F U
UDQM
CLK
CKL
N .C
A 9
A
8
A7
A6
A5
A
4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VCC1
MUTE
VIN1
VG1
VO1+
VO1-
(NC)
(NC)
VO2-
VO2+
VG2
VIN2
REG_C
REG_B
RESET Power supply (VCC2, short-circuit 28pin)
Output ON/OFF terminal
CH1, Input terminal
CH1, Input terminal(Gain setting)
CH1, Output te)
CH1, Output terminal(-)
(Do not use)
(Do not use)
CH2, Output terminal(-)
CH2, Output te)
CH2, Input terminal(Gain setting)
CH2, Input terminal
External PNP Connect to transistor collector
External PNP Connect to transistor base
RESET output
PIN No. Pin Name Description (Function) PIN No. Pin Name Description (Function)
16
17
18
19
20
21
22
23
24
25
26
27
28
CD
VIN3
VG3
VO3+
VO3-
(NC)
(NC)
VO4-
VO4+
VG4
VIN4
VREF
VCC2
RESET Connect to condenser
of dalay time setting
CH3, Input terminal(Gain setting)
CH3, Input terminal(Gain setting)
CH3, Output te)
CH3, Output terminal(-)
(Do not use)
(Do not use)
CH4, Output terminal(-)
CH4, Output te)
CH4, Input terminal(Gain setting)
CH4, Input terminal(Gain setting)
Standard applied voltage terminal
Power supply
(VCC1, short-circuit 1pin)
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except CLK,CKE
and L(U)DQM.
Makes system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
System Clock
Chip Enable
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
CLK
CS
CKE
A0~A10/AP
BA
RAS
CAS
WE
L(U)DQM
PIN NAME Input Function
IC104 LA6548NH-E (CD Driver)