Samsung SGH-P960, Руководство по обслуживанию

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SAMSUNG Proprietary-Contents may change without notice
Flow Chart of Troubleshooting
9-43
This Document can not be used without Samsung's authorization
VREG_BT_2.6V
GPIO_2|WLAN_TX_CONFX
8
GPIO_3
9
D
N
G
53
D
N
G
63
D
N
G
73
D
N
G
83
FM_AUDIO_L
4
WLAN_BT_ACTIVITY|A_GPIO_5
5
HOST_WAKE|GPIO_1
6
BT_WAKE|GPIO_0
7
PCM_IN
28
PCM_CLK
29
D
N
G
3
PCM_SYNC
30
GPIO_7
31
UART_RTS
32
UART_CTS
33
UART_RX
34
VREG_CTRL
20
V3
R
D
D
V
12
F
R_
D
D
V
22
M
F_
D
D
V
32 42
C
D
D
V
RST_N
25
PCM_OUT
26
OI
_
D
D
V
72
D
N
G
31
T
B_
T
N
A
41
D
N
G
51
TM0
16
71
M
F_
T
N
A
GPIO_4
18
LPO_CLK
19
FM_AUDIO_R
2
U100
UART_TX
1
WLAN_BT_PRIORITY_AND_STATUS|A_GPIO_4
10
I2C_DATA
11
I2C_CLK
12
TA102 TA101
C111 C112
C109
C105 C104
L105
C103
ANT102
1 2
0
L104
C119
L101
00
1
D
R100
BT_PCM_DOUT
BT_PCM_DIN
BT_PCM_SYNC
BT_UART_CTS
BT_UART_RTS
BT_UART_TX
BT_UART_RX
AFL
AFR
BT_WAKE
HOST_WAKE
SLEEP_XTAL_IN
BT_RESET
BT_SLEEP
R_ANT
I2S_FM_RL
I2S_FM_DOUT
I2S_FM_CLK
BT_PCM_CLK
R414
L402
R415
TP_RF_TCXO
C433
L2
VIB_DRV_N
L3
KPD_PWR_N
L4
C
M
S
M
_
D
D
V
5
L
VREG_S3
L6
3
2
S_
D
D
V
7
L
VREG_S2
L8
VREG_MMC
L9
K5
VSW_S3
K6
VSW_S2
K7
VREG_MSME
K8
SLEEP_CLK
K9
MPP4|LCD_DRV_N
L1
VREG_RUIM
L10
XTAL_IN
L11
MPP3|KPD_DRV_N
J11
USB_D_P
J2
HSET_BIAS
K1
MI
U
R
_
D
D
V
01
K
XTAL_OUT
K11
MPP7|CBLPWR_N
K2
AMUX_OUT
K3
VREG_MSMC
K4
VSW_MSMC
H2
USB_SE0
H4
MPP12|RUIM_IO
H5
MPP10|RUIM_CLK
H6
MPP6|RUIM_RST
H7
OPT_2
H8
USB_D_M
J1
VCOIN
J10
VREG_MSMP
G4
D
N
G
5
G
D
N
G
6
G
D
N
G
7
G
SBDT|SSBI
G8
USB_VBUS
H1
TCXO_OUT_1
H10
M
S
M
_
D
D
V
11
H
USB_ID
5
F
D
N
G
6
F
D
N
G
7
F
SBCK
F8
V5
_
G
E
R
V
1
G
PON_RESET_N
G10
VREG_MSMA
G11
VREG_USB
G2
USB_DAT
6
E
D
N
G
7
E
SBST
E8
V
5
_
W
S
V
1
F
PS_HOLD
F10
TCXO_OUT_RF
F11
USB_OVP_G
F2
USB_OE_N
F4
D
N
G
D7
TCXO_EN_1
D8
T
A
B
V
1
E
REF_GND
E10
TCXO_IN
E11
BAT_FET_N
E2
TCXO_EN_2
E4
D
N
G
5
E
D
N
G
C2
ISNS_M
D1
REF_ISET
D10
C
N
D
1
1
D
ISNS_P
D2
OPT_1
D4
MPP11|RUIM_M_IO
D5
MPP9|RUIM_M_CLK
D6
MPP5|RUIM_M_RST
B5
SPKR_IN_P
B6
MPP2|AMUX_IN2
B7
VREG_RFUBM
B8
F
R
_
D
D
V
9
B
VCHG
C1
MSM_INT_N
C10
REF_BYP
C11
CHG_CTL_N
A8
VREG_RFRX1
A9
VREG_GP3
B1
TCXO_OUT_2
B10
VREG_WLAN
B11
NI
A
M
_
D
D
V
2
B
P
G_
D
D
V
3
B
MPP8|REF_OUT
B4
SPKR_IN_M
A10
N
A
L
W
_
D
D
V
11
A
VREG_GP2
A2
VREG_GP1
A3
R
K
P
S
_
D
D
V
4
A
SPKR_OUT_M
A5
SPKR_OUT_P
A6
MPP1|AMUX_IN1
A7
VREG_RFTX
U401
C
N
1
C
N
2
VREG_TCXO
A1
VREG_RFRX2
R424
u
p
D
P
p
n_
3
P
D
Pk
_3
P
P2_B
P2_B
AO
P3_npPDpu
P2_B
P3H_HnppdPU
U
P-
SI
_3
P
P2_O
P1_nppdPU
u
p
D
P
p
n_
1
P
P4H_HnpPDpu
u
p
D
P
p
n_
3
P
P4H_HnpPDpu
P1_B-K
P2_B-K
P1_O
Vdd_mddi
AI
P1_B-K
u
p
D
P
p
n_
3
P
P2_B-K
P2_O
U
P
d
p
p
n_
3
P
Vdd_mddi
P2_nppdPU
P2_B-K
P1_B-K
u
p
D
P
p
n_
3
P
P2_O
P1_B-K
P2_O
AI
D
P-
SI
_3
P
U
P
d
p
p
n_
3
P
AI
P1_B-K
P3_IS-PD
P2_nppdPU
P3H_HnppdPU
P2_B-K
P1_B-K
U
P
d
p
p
n_
3
P
P1_O
P3_npPDpu
P2_B
P4H_HnpPDpu
P1_IS
P3_AO
P2_B
P3_B-K
P2_B
P1_B-K
P1_B-K
P2_B
P2_O
P3_IS-PD
AO
P1_B-K
P1_B-K
AI
P2_B
P2_B-K
P2_O
P1_nppdPU
P3_npPDpu
P1_B-K
P1_B-K
AO
K-
B_
3
P
P1_B-K
P1_BS-PU
P2_B-K
P3_O
P3_B-K
K-
B_
3
P
P3H_HnppdPU
P1_O
P1_B-K
P3_IS
P1_O
AI
AI
AI
P1_B-K
P1_B-K
P2_B-K
AI
P1_B-K
O
A
P1_B-K
P1_B-K
AI
P3_IS
P3_nppdPU
P1_B-K
P3_npPDpu
P3H_HnppdPU
P3_AO
P2_B-K
P2_B-K
Vdd_mddi
P1_B-K
P1_npPDpu
P3_npPDpu
P4H_HnpPDpu
P2_npPDpu
U
P
d
p
p
n_
3
P
U
P
d
p
p
n_
3
P
P3_nppdPU
P2_nppdPU
P1_B-K
P1_B-K
P3H_HnppdPU
P1_B-K
K-
B_
3
P
P2_B
P3_nppdPU
P1_BS-PU
P1_B-K
P2_B
AI
P1_O
P1_B-K
P2_B-K
P1_B-K
P1_B-K
P4H_HnpPDpu
P3_IS-PD
U
P-
SI
_3
P
P3_nppdPU
P4H_HnpPDpu
P2_B
U
P-
SI
_3
P
P3_npPDpu
P1_O
P1_O
U
P
d
p
p
n_
3
P
AI
P1_B-K
P1_B-K
P2_O
AO
K-
B_
3
P
U
Pd
p
p
n_
3
P
P3_AO
P3_IS
AI
AI
P3_AI
AO
P3_O
u
p
D
P
p
n_
3
P
P3_npPDpu
u
p
D
P
p
n_
3
P
U
P
d
p
p
n_
3
P
P4H_HnpPDpu
Vdd_mddi
AI
P3_nppdPU
Vdd_mddi
Vdd_mddi
P3_O
P3_nppdPU
P2_B
P3_npPDpu
P3H_HnppdPU
P1_B-K
P3_IS-PU
P1_B-K
u
p
D
P
p
n_
3
P
P3_nppdPU
P1_B-K
P1_B-K
K-
B_
3
P
P3_npPDpu
AI
P3_AO
AI
P3_nppdPU
P3_npPDpu
AI P1_B-K
P1_O
P1_npPDpu
Z
_3
P
P1_B-K
AI
u
p
D
P
p
n_
3
P
D
Pk
_3
P
P1_B-K
D
P
k_
3
P
AI
u
p
D
P
p
n_
3
P
P2_B
P2_B-K
u
p
D
P
p
n_
3
P
P1_B-K
u
p
D
P
p
n_
3
P
P1_B-K
P2_B
P1_O
P3_AO
P1_O
AO
P1_O
P3_nppdPU
P2_B
D
Pk
_3
P
P3_nppdPU
P3_nppdPU
P2_B-K
P2_B
P3_nppdPU
P1_B-K
P2_B-K
U
P
d
p
p
n_
3
P
P3_nppdPU
P3_nppdPU
P3_npPDpu
K-
B_
3
P
P3_Znppdpu
P2_B-K
P1_B-K
P2_nppdPU
P3_nppdPU
u
p
D
P
p
n
_3
P
P2_nppdPU
P1_B-K
P4H_HnpPDpu
P3_npPDpu
AI
O
A_
3
P
u
p
D
P
p
n_
3
P
AO
P3_nppdPU
AO
AI
AO
P3_npPDpu
AI
P3_npPDpu
P2_npPDpu
P3_Znppdpu
P2_B
P2_B-K
I
A_
3
P
D
Pk
_3
P
P2_B-K
P3_nppdPU
AI
P2_B
D
Pk
_3
P
P1_B-K
D
Pk
_3
P
P3_Znppdpu
P3_Znppdpu
K-
B_
3
P
P3_nppdPU
P3_AO
P3_npPDpu
P2_nppdPU
AI
P1_B-K
Vdd_mddi
AI
K-
B_
3
P
P1_B-K
AI
Vdd_mddi
AI
O
_3
P
P3_B-K
AO
U
P
d
p
p
n_
3
P
Place near pin AA20
U
P
d
p
p
n_
3
P
P3_npPDpu
C357
8
0
3
R
C302
R312
VDDA
Y25
SDRAM1_D4|D1_4
Y4
SDRAM1_D2|D1_2
Y5
D
N
G
7
W
D2_2
W8
D2_8
W9
XMEM1_CS_N1|GPIO76
Y1
SDRAM1_D20|GPIO71
Y2
MODE0
Y21
HKAIN5
Y22
Q_IM_CH0
Y24
D
N
G
91
W
VDD_DIG2
W2
HKAIN4
W21
HKAIN1
W22
Q_IP_CH0
W24
VDDA
W25
XMEM1_CS_N3|GPIO77|SDRAM1_CS_N1
W4
RESOUT_N_EBI1
W5
D2_13
W11
A2_8
W12
A2_15
W13
XMEM2_CS_N0|NAND1_CS_N
W14
XMEM2_CS_N2|GPIO35
W15
VSSA W16
HPH_L
W17
VSSA
W18
VSSA
V25
XMEM1_CS_N0|SDRAM1_CS_N2
V4
XMEM1_HWAIT_N|SDRAM1_CLK_EN1
V5
MDP_VSYNC_PRIMA_RY|GPIO105
V7
D
N
G
8
V
D
N
G
9
V
VSS_DIG2
W1
D2_12
W10
MICBIAS
V16
D
N
G
71
V
D
N
G
81
V
D
N
G
91
V
OE1_N|SDRAM_CLK_EN2
V2
HKAIN0
V21
Q_IM_CH1
V22
I_IP_CH1
V24
D
N
G
8
U
A1_24|GPIO79SDRAM1_A0
V1
D2_5
V10
D2_9
V11
A2_3
V12
A2_7
V13
A2_18|D216ADV_N
V14
NAND2_FLASH_READY|GPIO33|EBI2_PNAND_READY
V15
VDD_PAD14
U2
KEYSENSE4_N|GPIO48|ETM_TRACE_PKT2
U21
Q_IP_CH1
U22
I_IM_CH1
U24
VSSA
U25
SDRAM1_D23|GPIO74|EBI1_HUB_N
U4
XMEM1_CS_N2|SDRAM1_CS_N0
U5
SDRAM1_D22|GPIO73|EBI1_HLB_N
U7
VDDA
T25
SDRAM1_D17|GPIO68
T4
2
M
Q
D_
1
M
A
R
D
S|
32
_
1
A|
87
OI
P
G
5
T
SDRAM1_D16|GPIO67
T7
A1_25|GPIO75|SDRAM1_DQM3
T8
VSS_PAD14
U1
D
N
G
81
U
HKAIN3
U19
WE1_N|SDRAM1_WE_N
R8
A1_17|SDRAM1_D26
T1
VDD_QFUSE
T18
VSSA
T19
A1_18|SDRAM1_D27
T2
GPIO9|GRFC6
T21
MODE1
T22
VDDA
T24
VDD_PAD13
R2
8
T
K
P_
E
C
A
R
T_
M
T
E
A
T
A
D_
T
B|
02
OI
P
G
12
R
MODE2
R22
VDD_DIG6
R24
VSS_DIG6
R25
A1_21|SDRAM1_D30
R4
A1_20|SDRAM1_D29
R5
A1_22|SDRAM1_D31
R7
VSS_PAD13
R1
D
N
G
11
R
D
N
G
21
R
D
N
G
31
R
D
N
G
41
R
D
N
G
51
R
UART1_CTS_N|GPIO97
R18
KEYSENSE0_N|GPIO62|KYPD_1|ETM_PIPESTAT0
R19
KEYSENSE3_N|GPIO47|KYPD_7|ETM_TRACE_PKT1
P21
GPIO10|GRFC7
P22
VDD_PAD30
P24
VSS_PAD30
P25
A1_15|SDRAM1_D24
P4
A1_16|SDRAM1_D25
P5
A1_13
P7
SDRAM1_D18|GPIO69
P8
D
N
G
11
P
D
N
G
21
P
D
N
G
31
P
D
N
G
41
P
D
N
G
51
P
PA_ON2|GPIO29|BM_INT|TSIF_SYNC
P18
KENSENSE1_N|GPIO63|KEYSENSE1_N|KYPD_3
P19
A1_11
P2
VDDA
N22
L
T
C_
R
E
W
O
P_
A
P
42
N
VSSA
N25
SDRAM1_D8|D1_8
N4
A1_12
N5
A1_7
N7
A1_19|SDRAM1_D28
N8
A1_10
P1
D
N
G
21
N
D
N
G
31
N
D
N
G
41
N
D
N
G
51
N
L
C
S_
C2I
|7
2
OI
P
G
81
N
M_
L
T
C_
R
E
W
O
P_
A
P
91
N
A1_8
N2
USB_SE0_VM
N21
USB_OE_TP_N
M24
USB_DAT_VP
M25
SDRAM1_CLK_EN0
M4
A1_5
M5
A1_6
M7
A1_14
M8
A1_9
N1
D
N
G
11
N
D
N
G
31
M
D
N
G
41
M
D
N
G
51
M
RINGER|GPIO18|CAMIF_EN
M18
UART3_DP_TX_DATA|GPIO84|TSIF_ERROR|TSIF_NULL|TSIF_SYNC|PM_SBCK
M19
VDD_PAD12
M2
UART3_DP_RX_DATA|GPIO85|TSIF_DATA|PM_SBST
M21
L
L
U
N_
FI
S
T|
9
T
K
P_
E
C
A
R
T_
M
T
E|
31
C
F
R
G|
K
L
C
M_
C
A
D
S|
NI
D_
M
C
P
_
X
U
A|
41
OI
P
G
2
2
M
SDCC_DAT3|GPIO101
L25
UB1_N|SDRAM1_DQM1
L4
A1_4
L5
A1_2
L7
A1_3
L8
VSS_PAD12
M1
D
N
G
11
M
D
N
G
21
M
D
N
G
41
L
D
N
G
51
L
SDCC_CLK|GPIO31|MMC_CLK
L18
L
L
U
N_
FI
S
T|
C
N
Y
S_
FI
S
T|
C
N
Y
S_
FI
S
T|
41
C
F
R
G|
01
T
K
P
_
E
C
A
R
T_
MT
E|
K
L
C_
M
C
P
_
X
U
A|
08
OI
P
G
91
L
LB1_N|SDRAM1_DQM0
L2
A
T
A
D
_2I
B
S
S|
K
C
B
S
12
L
UART1_DP_RX_DATA|GPIO96
L22
SDCC_DAT2|GPIO100
L24
UART1_DP_TX_DATA|GPIO95|NAND_BOOT_ERR
K25
SDRAM1_D15|D1_15
K4
SDRAM1_D13|D1_13
K5
SDRAM1_D14|D1_14
K7
XMEM1_LWAIT_N|SDRAM1_CAS_N
K8
A1_1
L1
D
N
G
21
L
D
N
G
31
L
D
N
G
8J
VSS_PAD11
K1
11
T
K
P_
E
C
A
R
T
_
M
T
E|
5
A
T
A
D
_
FI
M
A
C|
75
OI
P
G
81
K
SDCC_DAT1|GPIO99
K19
VDD_PAD11
K2
A
D
S_
C2
I|
62
OI
P
G
12
K
UART3_CTS_N|GPIO86|TSIF_ENABLE|PM_SBDT
K22
UART3_RFR_N|GPIO87|TSIF_CLK
K24
SDRAM1_D10|D1_10
J2
O
P_
K
L
C
M
A
C|
K
L
C_
P
G|
N
M_
P
G|
31
OI
P
G
12
J
K
L
C
P
_
FI
M
A
C|
28
OI
P
G
22
J
VDD_PAD31
J24
GI
R
T_
M
D
M_
M
B|
L
L
U
N_
FI
S
T|
T
E
S
E
R
_
FI
M
A
C|
71
OI
P
G
52
J
SDRAM1_D9|D1_9
J4
SDRAM1_D11|D1_11
J5
SDRAM1_D7|D1_7
J7
SDRAM1_D0|D1_0
H4
SDRAM1_D5|D1_5
H5
11
C
F
R
G|
R_
L_
C
A
D
S|
C
N
Y
S_
M
C
P_
X
U
A|
20
1
OI
P
G
7
H
D
N
G
8
H
D
N
G
9
H
SDRAM1_D12|D1_12
J1
D
N
G
81
J
1
1
T
K
P
_
E
C
A
R
T_
M
T
E|
N_
X
R
_
X
T_
T
B|
12
OI
P
G
91
J
D
N
G
71
H
D
N
G
81
H
21
T
K
P_
E
C
A
R
T
_
M
T
E|
T
D
B
S_
T
B|
22
OI
P
G
91
H
VDD_DIG1
H2
5
1
T
K
P
_
E
C
A
R
T_
M
T
E|
KL
C_
T
B|
52
OI
P
G
12
H
A
T
A
D_
0I
B
S
S|
T
D
B
S
22
H
0
A
T
A
D
_
FI
M
A
C|
38
OI
P
G
4
2
H
1
A
T
A
D
_
FI
M
A
C|
18
OI
P
G
52
H
VSS_DIG1
H1
GPIO43|ETM_PIPESTAT1B
H10
GPIO49|KYPD_9|ETM_TRACE_PKT3
H11
5
C
F
R
G|
8
OI
P
G
21
H
TRK_LO_ADJ
H13
GPIO64|UART1_RI|ETM_PIPESTAT2
H14
21
T
K
P_
E
C
A
R
T
_
M
T
E|
6
A
T
A
D
_
FI
M
A
C|
85
OI
P
G
5
1
H
UART1_RFR_N|GPIO93|SBST1
H16
14
OI
P
G
22
G
WDOG_STB|GPIO_0|SBCK1
G24
A
T
A
D_
1I
B
S
S|
T
S
B
S
52
G
SDRAM1_D1|D1_1
G4
UART2_DP_RX_DATA|USIM_PWR_EN|GPIO89
G5
D
N
G
7
G
GPIO40|PM_INT_N
G8
GPIO66|MONO_STEREO_HS_DET_N|ETM_TRACECLK
G9
SDCC_CMD|GPIO30|MMC_CMD
G14
S
M
T
51
G
41
T
K
P_
E
C
A
R
T
_
M
T
E|
8
A
T
A
D
_
FI
M
A
C|
06
OI
P
G
61
G
PA_RANGE0|GP_PDM1
G17
0
M
D
P_
P
G|
29
OI
P
G
81
G
D
N
G
9
1
G
SDRAM1_D6|D1_6
G2
9
T
K
P_
E
C
A
R
T
_
M
T
E|
3
A
T
A
D
_
FI
M
A
C|
55
OI
P
G
12
G
VSS_DIG7
F25
UART2_CTS_N|USIM_RESET|GPIO90
F4
UART2_DP_TX_DATA|USIM_DATA|GPIO88
F5
ROM1_ADV_N|SDRAM1_RAS_N
G1
GPIO52|KYPD_15|ETM_TRACE_PKT6
G10
PA_ON1|GPIO2
G11
RESOUT_N
G12
RESIN_N
G13
GPIO11|GRFC8
E7
GPIO42|PS_HOLD|ETM_PIPESTAT2B
E8
4
C
F
R
G|
7
OI
P
G
9
E
VSS_PAD10
F1
VDD_PAD10
F2
C
N
Y
S
H
_
FI
M
A
C|
51
OI
P
G
12
F
41
T
K
P_
E
C
A
R
T_
M
T
E|
T
S
B
S_
T
B|
42
OI
P
G
22
F
VDD_DIG7
F24
D
N
G
02
E
D
N
G
12
E
K
L
C_
P
G|
91
OI
P
G
22
E
31
T
K
P_
E
C
A
R
T_
M
T
E|
K
C
B
S_
T
B|
32
OI
P
G
42
E
1
OI
P
G|
1
T
D
B
S
52
E
21
C
F
R
G|
T
U
O
D
_
C
A
D
S|
T
U
O
D_
M
C
P_
X
U
A|
30
1
OI
P
G
4
E
D
N
G
5
E
C
N
Y
S
V
_
FI
M
A
C|
61
OI
P
G
6
E
TX_AGC_ADJ
E13
SDCC_DAT0|GPIO32|MMC_DATA
E14
N_
T
S
R
T
51
E
PA_ON0
E16
VSSA
E17
8
T
K
P_
E
C
A
R
T
_
M
T
E|
2
A
T
A
D
_
FI
M
A
C|
45
OI
P
G
81
E
51
T
K
P_
E
C
A
R
T
_
M
T
E|
9
A
T
A
D
_
FI
M
A
C|
16
OI
P
G
91
E
SDRAM1_D3|D1_3
E2
GPIO12|GRFC9
D6
GPIO39|UART1_DCD
D7
GPIO44|UART1_DTR|ETM_PIPESTAT0B|GP_CLK
D8
GPIO5|GRFC2
D9
SDRAM1_D19|GPIO70
E1
GPIO6|GRFC3
E10
TX_ON|GRFC10
E11
VDDA
E12
VDD_DIG0
D2
TCXO_EN|GPIO94
D20
31
T
K
P_
E
C
A
R
T
_
M
T
E|
7
A
T
A
D
_
FI
M
A
C|
95
OI
P
G
12
D
D
N
G
22
D
VDD_DIG8
D24
VSS_DIG8
D25
D
N
G
4
D
GPIO45|KYPD_MEMO|ETM_TRACESYNC_B
D5
DAC_REF
D12
KEYSENSE2_N|GPIO46|KYPD_5|ETM_TRACE_PKT0
D13
I
D
T
41
D
K
C
T
5
1
D
K
C
T
R
61
D
PA_RANGE1|GP_PDM2
D17
TCXO
D18
01
T
K
P_
E
C
A
R
T
_
M
T
E|
4
A
T
A
D
_
FI
M
A
C|
65
OI
P
G
91
D
USB_XTAL48_OUT
B9
D
N
G
1
C
UART2_RFR_N|USIM_CLK|GPIO91
C2
RESERVED
C24
D
N
G
52
C
VSS_DIG0
D1
GPIO53|KYPD_17|ETM_TRACE_PKT7
D10
VSSA
D11
D
N
G
42
B
D
N
G
52
B
VDD_PAD40
B3
VDD_DIG12
B4
C
N
Y
S
E
C
A
R
T
_
M
T
E|
56
OI
P
G
5
B
GPIO50|KYPD_11|ETM_TRACE_PKT4
B6
GPIO3|GRFC0
B7
VDD_PAD33
B8
VDD_PLL
B17
MDDIH_DATN
B18
MDDIH_DATP
B19
D
N
G
2
B
VDD_PAD15
B20
MDDIC_DATP
B21
MDDIC_DATN
B22
VSS_DIG9
B23
D
N
G
1
B
VDD_DIG11
B10
I_OUT
B11
I_OUT_N
B12
VDD_DIG10
B13
VDD_PAD32
B14
SLEEP_XTAL_OUT
B15
VSS_PAD31
B16
D
N
G
52
E
A
D
N
G
3
E
A
WE2_N
AE4
VSS_PAD20
AE5
OE2_N|NAND2_RE_N
AE6
VSS_DIG4
AE7
UB2_N|NAND2_CLE
AE8
VSS_PAD21
AE9
MIC1P
AE18
MIC2N
AE19
D
N
G
2
E
A
MIC2P AE20
VSSA
AE21
VSSA
AE22
D
N
G
32
E
A
D
N
G
42
E
A
A2_12
AE10
A2_20|GPIO34LCD_RSEBI2_HLB_N
AE11
LCD_CS_N|GPIO38
AE12
VSS_PAD22
AE13
VSS_DIG5
AE14
EAR1ON
AE15
EAR1OP AE16
MIC1N
AE17
D2_1
AD3
D2_6
AD4
VDD_PAD20
AD5
D2_11
AD6
VDD_DIG4 AD7
LB2_N|A2_0|NAND2_ALE
AD8
VDD_PAD21
AD9
D
N
G
1
E
A
BOOT_MODE1
AD19
D
N
G
2
D
A
BOOT_MODE2
AD20
VDDA
AD21
VDDA
AD22
HKAIN2
AD23
D
N
G
42
D
A
D
N
G
52
D
A
LCD_EN|GPIO37|HUB_N
AD11
A2_16
AD12
VDD_PAD22
AD13
VDD_DIG5
AD14
WDOG_EN
AD15
VDDA
AD16
AUXIN
AD17
AUXIP
AD18
D2_14
AB8
A2_4
AB9
D
N
G
1
C
A
BOOT_MODE3
AC2
VSSA
AC24
D
N
G
52
C
A
D
N
G
1
D
A
A2_11
AD10
LINE_R_IP
AB21
VSS_DIG13
AB22
I_IP_CH0
AB24
VSSA
AB25
D
N
G
4
B
A
D2_3
AB5
D2_4
AB6
D2_10
AB7
XMEM2_CS_N1|NAND2_CS_N
AB14
VSSA
AB15
LINE_OP
AB16
LINE_ON
AB17
LINE_L_IN
AB18
LINE_L_IP
AB19
VDD_DIG3
AB2
LINE_R_IN
AB20
D2_7
AA7
D2_15
AA8
A2_2
AA9
VSS_DIG3
AB1
A2_6
AB10
A2_10
AB11
A2_14
AB12
A2_17
AB13
CCOMP
AA20
D
N
G
12
A
A
F
E
R_
C
A
D_
A
P
_
M
S
G
22
A
A
I_IM_CH0
AA24
VSSA
AA25
MDP_VSYNC_SECON_DARY|GPIO104
AA4
D
N
G
5
A
A
D2_0
AA6
A2_13
AA13
A2_19|D217WAIT_N
AA14
XMEM2_CS_N3|GPIO36
AA15
VDDA
AA16
HPH_R
AA17
AUXOUT
AA18
HPH_VREF
AA19
SDRAM1_D21|GPIO72
AA2
GPIO51|KYPD_13|ETM_TRACE_PKT5
A6
1
C
F
R
G|
4
OI
P
G
7
A
VSS_PAD33
A8
USB_XTAL48_IN
A9
ROM1_CLK|SDRAM1_CLK
AA1
A2_1
AA10
A2_5
AA11
A2_9
AA12
MDDIC_STBP
A21
MDDIC_STBN
A22
VDD_DIG9
A23
D
N
G
42
A
D
N
G
52
A
D
N
G
3
A
VSS_DIG12
A4
82
OI
P
G
5
A
VSS_PAD32
A14
SLEEP_XTAL_IN
A15
O
D
T
61
A
VSSA
A17
MDDIH_STBN
A18
MDDIH_STBP
A19
D
N
G
2
A
VSSA
A20
C
N
1
C
N
2
L
A
M
R
E
H
T
_
S
S
V
1
A
VSS_DIG11
A10
Q_OUT_N
A11
Q_OUT
A12
VSS_DIG10
A13
UCP300
C353
R313
C354
R306
R311
SDRAM_BA1
SDRAM_BA0
C400
1
0
4
C
2
0
4
C
3
0
4
C
4
0
4
C
C405
6
0
4
C
9
0
4
C
0
1
4
C
1
1
4
C
2
1
4
C
3
1
4
C
4
1
4
C
5
1
4
C
C416
C417
8
1
4
C
9
1
4
C
C420
1
2
4
C
C422
C423
C424 C425
6
2
4
C
7
2
4
C
C428
9
2
4
C
0
3
4
C
1
3
4
C
C433
4
3
4
C
D400
D401
0
0
4
L
L401 L402
0
0
4
C
S
O
PM _IN T
0
0
4
R
1
0
4
R
R403
5
0
4
R
6
0
4
R
7
0
4
R
8
0
4
R
9
0
4
R
0
1
4
R
1
1
4
R R412
3
1
4
R
4
1
4
R
R415
R416
7
1
4
R
R418
9
1
4
R
3
2
4
R
4
2
4
R
5
2
4
R
1
3
4
R
6
0
1
C
S
SC 114
TP _R F_ TC XO
1
0
4
U
U601