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7. Block Diagrams
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[SGH-P960] Baseband Block Diagram
MSMC
MSME
MSMA
MSMP
TFLASH
USIM
RF_S2
RF_S3
TCXO
USB
BT
JIG_ON_SW
SDRAM (1G)
SLEEP_XTAL_IN
3M CAM
ADC_BOOT_SW
AMUX_OUT
CHG_EN_N
19.2M
TCXO
PS_HOLD
PM6658
Charging IC
Samsung Memory
MODEM
(MSM6280_NSP)
VLCD_2.8V
MCAM_1.8V
IO/A_2.8V
TCXO_OUT
Backend CHIP
SH7363
CIF CAM
VCAM_1.8V
IO/A_2.8V
2.6" QVGA LCD
( 320*240, 18bit CPU type )
LCD_RST
A1(0:12)/D1(0:31)
32.768KHz
VCOIN
TCXO
TCXO_EN
Flash LED
Boost
Converter
MOTOR
MOT_3.3V
I2C_SCL/SDA
CAM_D(0:7)/VSYNC/HSYNC
CAM_MCLK/PCLK
KEY CIRCUIT
S20 EAR L/R
BT
MODULE
TRST_N
PS_HOLD
VCAM_EN/RESET_N
SIM_RST_PMIC
SIM_CLK_PMIC
SIM_IO_PMIC
BT_UART_CTS/RTS/TX/RX
USB_DP/DM
USB_OE_N/DAT/SEO
SIM_CLK/RST/IO
EBI1
EBI2
OneNAND Flash (2G)
BT_ANT
EAR_SW/JACK_INT
ADC_BOOT_SW
EARMIC_P/N
From MV8720
USB_DP/DN
IF_UART1_TX/RX
JTAG_UART1_RX/TX
JTAG_JIG_ON
A2(1:16)/D2(0:15)
SDRAM_BA0,1/RAS_N/CAS_N
SDRAM_WE_N/CLK/CKE
SDRAM_CS/DQM(0:3)
WE2_N/OE2_N
NANDFLASH_CS/READY
RESOUT_N_EBI1
WE2_N/OE2_N/SLEEP_XTAL_IN
A2(1:4)/D2(0:15)
REF_OUT
TFLASH_DATA(0:3)
VREG_MSME_1.8V
JTAG
RTCK/TDO
TMS/TRST_N
TCK/TDI
RESET_N
1.2V
2.8V
3.0V
1.8V
2.6V
3.3V
2.6V
2.1V
2.7V
2.85V
2.6V
SSIB2_DATA
EAR_SW
PM_INT_N
RESET_N
VBATT_4.2V
USB
Filter
USB_D_P/M
JIG_ON
CHG_DETECT_N/ICHRG
BT_PCM_CLK/DOUT/DIN/SYNC
BT_SLEEP/RESET
BT_WAKE/HOST_WAKE
AFL/AFR
FM_ANT
MOTOR_EN
TFLASH_CMD/CLK/DET
HALL_IC
MSMP_2.6V
HALL_SW
LCD_D2(0:17)
LCD_CS_N/WE_N
LCD_RS/MODE_SEL
FRAME_SYNC
Backlight
Driver IC
And LDO
LED+
LED(-)1/2/3/4
FLASH_LED_EN
FLASH_MODE_EN
MCAM_EN/RESET_N
CMC530S2_SSP
PHONE_ON
LDO
VBATT_4.2V
KEY_LED_EN
VDD_KEY
_3.3V
KEYSENSE(0:4)
KYPD(9)/(11)/(13)/(15)/(17)/MEMO
VBATT_4.2V
SAPA2
VBATT_4.2V
VREG_AUDIO_1.8V
VREG_MSMP_2.6V
SAPA2_I2C_SCL/SDA
SAPA2_PCM_CLK/DOUT/SYNC
AUDIO_CLK
SDAC_L_R_N
SDAC_CLK/DOUT
SPK_N/P
SAPA2_PWDN
TCXO_OUT
SH
JTAG
SH_TMS/TCK/
TRST_N/TDI
SH_TDO/MPMD
ASEBRK
SH_CS_N/IRQ
MSM2SH_IRQ
TO MEMORY
D2(0:15)
SH_STATUS0
DVB_SPI_EN/CLK
DVB_SPI_MISO/MOSI
DVB_INT
DVB_ANT
DVB_RESET_N
LDO
LDO
SH_VCCQ1_1.8V
SH_VDD_1.2V/2.8V
SH_VDD_2.8V
VDD_PLL_1.2V
DVB_PWR_ON
DVB_1.2V/1.8V/2.8V
DVB_1.2V_AL