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SGH-P400 Circuit Description
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motor voltage of 1.1V to 2.5V in 20mV steps and while sinking up to 100mA.
For efficient use, the vibrator motor should be connected between the main
battery and the VIB_DRV output.
5) Memory
This system uses SHARP's
memory, LRS1828A.
It is consisted of 128M bits flash memory and32M bits psuedo SRAM. It has
16 bit data line, D[0~15] which is connected to trident, LCD or CSP1093. It
has 22 bit address lines, A[1~22]. They are connected too. CP_CSROMEN and
CO_CSROM2EN signals, chip select signals in the trident enable two memories.
They use 3 volt supply voltage, V_ccd and 1.8 volt supply voltage, Vcc_1.8a in
the PSC2106. During wrting process, CP_WEN is low and it enables writing
process to flash memory and pseudo SRAM. During reading process, CP_OEN
is low and it output information which is located at the address from the
trident in the flash memory or SRAM to data lines. Each chip select signals in
the trident select memory among 2 flash memory and 2 SRAM. Reading or
writing procedure is processed after CP_WEN or CP_OEN is enabled. Memories
use FLASH_RESET, which is buffered signal of RESET from PSC2106, for ESD
protection. A[0] signal enables lower byte of pseudo SRAM and UPPER_BYTE
signal enables higher byte of pseudo SRAM.
6) Trident
Trident is consisted of ARM core and DSP core. It has 20K*16bits RAM
144K*16bits ROM in the DSP. It has 4K*32bits ROM and 2K*32bits RAM in the
ARM core. DSP is consisted of timer, one bit input/output unit(BIO), JTAG, EMI
and HDS(Hardware Development System). ARM core is consisted of EMI,
PIC(Programmable Interrupt Controller), reset/power/clock unit, DMA controller,
TIC(Test Interface Controller), peripheral bridge, PPI, SSI(Synchronous Serial
Interface), ACC(Asynchronous communications controllers), timer, ADC,
RTC(Real-Time Clock) and keyboard interface.
DSP_AB[0~8], address lines of DSP core and DSP_DB[0~15], data lines of
DSP core are connected to CSP1093. A[0~20], address lines of ARM core and
D[0~15], data lines of ARM core are connected to memory, LCD and YMU759.
ICP(Interprocessor Communication Port) controls the communication between
ARM core and DSP core.
CSROMEN, CSRAMEN and CS1N to CS4N in the ARM core are connected to
each memory. WEN and OEN control the process of memory. External
IRQ(Interrupt ReQuest) signals from each units, such as, YMU, Ear-jack,
Ear-mic and CSP1093, need the compatible process.
