Samsung S5PV210, Руководство по конструкции аппаратуры

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S5PV210_HARDWARE DESING GUIDE REV 1.0
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7. OneNAND Controller
Overview
S5PV210 supports external 16-bit bus for OneNAND and Flex-OneNAND memory devices. The OneNAND controller
supports asynchronous and synchronous read/write bus operations. It also integrates its own dedicated DMA engine
and microsequencer to accelerate the OneNAND memory device operation.
7.1. Signal Description
Signal I/O Description Comment
Xm0ADDR[15:0] IO
Xm0ADDR[15:0] (ADDR Bus) outputs address during
memory read/write address phase, inputs data during
memory read data phase and outputs data during
memory write data phase.
Xm0DATA[15:0] IO
Xm0DATA[15:0] (Data Bus) outputs address during
memory read/write address phase, inputs data during
memory read data phase and outputs data during
memory write data phase.
ONANDXL_CSn[1:0] O
ONANDXL_CSn[0:1] (Chip Select) are activated when
the address of a memory is within the address region of
each bank. ONANDXL_CSn[0:1] can be assigned to
either SROMC or OneNAND controller by System
Controller SFR setting.
Active LOW.
ONANDXL_CSn[0] should be
connected to OneNand device
externally.
Xm0WEn O
Xm0WEn (Write Enable) indicates that the current bus
cycle is a write cycle.
Active LOW.
Xm0OEn O
Xm0OEn (Output Enable) indicates that the current bus
cycle is a read cycle.
Active LOW.
ONDXL_INT[0:1] I Interrupt inputs from OneNAND memory Bank 0, 1.
- ONDXL_INT[0] is connected to
OneNand device internally.
- 4.7Kohm external pull-up
ONDXL_AVD O
Address valid output.
Active LOW.
ONDXL_RPn O
System reset output for OneNAND memory.
Active LOW.
ONDXL_SMCLK O
Static memory clock for synchronous static memory
devices.
Must be less than 83MHz.
PmOndCEB I
OneNand memory signal. Should be connected to c110
chip select signal externally.