Circuit Operation Description
Samsung Electronics
5-11
5-2-2(B) FUNCTIONS OF PULSES
(1) X rising ramp pulse
Just before X rising ramp pulse is impressed, the last Y electrode sustain pulse of previous sub field is
impressed. The pulse causes sustain discharge. Consequently, positive wall charge is accumulated in X
electrode, and negative wall charge is accumulated in Y electrode. X rising ramp erases wall charge
produced by the last sustain discharge pulse using weak-discharge.
(2) Y rising ramp pulse
During Y rising ramp period, weak-discharge begins when external voltage of about 390V~400V is
impressed to Y electrode, and each gap voltage is equal to discharge start voltage. Sustaining the
weak-discharge, positive wall charge is accumulated in X electrode and address electrode, and nega-
tive wall charge is accumulated in Y electrode of the entire panel.
(3) Y falling ramp pulse
During Y falling ramp period, the negative wall charge in Y electrode accumulated by 200V of X bias
is used to erase positive wall charge in X electrode. Address electrode (0V) sustains most of the posi-
tive electric charge accumulated during rising ramp period so that it can maintain wall charge distrib-
ution beneficial to the upcoming address discharge.
(4) Y scan pulse
This is called the scan pulse, selecting each of Y electrodes on a one-line-at-a-time basis. In this case,
Vscan means the scan bias voltage. About 70 V (Vscan) voltage is impressed on the selected electrode
lines, while 0 V (GND) voltage is impressed on the other lines.
In the cells the address pulse (70V~75V) is impressed on, address discharge is occurred because nega-
tive wall charge is accumulated in Y electrode, positive wall charge is accumulated in address elec-
trode by the applied ramp pulse, and the sum of impressed voltage is greater than discharge start
voltage. Thus, because scan pulse and data pulse are impressed line by line, very long time is taken
for PDP addressing.
(5) 1st sustain pulse
The sustaining pulse always begins with the Y electrode. This is because when address discharge is
generated, positive wall voltage is generated on the Y electrodes. Because wall electric charge generat-
ed by address discharge is generally smaller than wall voltage generated by sustaining discharge, ini-
tial discharges have small discharge strength, and stabilization is usually obtained after 5~6 times dis-
charges, subject to variations depending on the structure and environment of electrodes. The purpose
of impressing the initial sustaining pulses long is to obtain stable initial discharges and generate wall
electric charges as much as possible.
Содержание PS42P2SBX/XEC
Страница 2: ...ELECTRONICS Samsung Electronics Co Ltd Nov 2002 Printed in Korea AA82 00157A...
Страница 19: ...Circuit Operation Description Samsung Electronics 5 3 5 1 2 D PDP PS 42 BLOCK DIAGRAM...
Страница 26: ...Circuit Operation Description 5 10 Samsung Electronics 5 2 2 SPECIFICATION OF DRIVE PULSES 5 2 2 A DRIVE PULSES...
Страница 32: ...Circuit Operation Description 5 16 Samsung Electronics 5 2 3 D DRIVER CIRCUIT DIAGRAM...
Страница 33: ...Circuit Operation Description Samsung Electronics 5 17 5 2 3 E DRIVER BOARD CONNECTOR LAYOUT...
Страница 34: ...Circuit Operation Description 5 18 Samsung Electronics...
Страница 35: ...Circuit Operation Description Samsung Electronics 5 19...
Страница 36: ...Circuit Operation Description 5 20 Samsung Electronics...
Страница 37: ...Circuit Operation Description Samsung Electronics 5 21...
Страница 38: ...Circuit Operation Description 5 22 Samsung Electronics...
Страница 39: ...Circuit Operation Description Samsung Electronics 5 23...
Страница 40: ...Circuit Operation Description 5 24 Samsung Electronics...
Страница 41: ...Circuit Operation Description Samsung Electronics 5 25...
Страница 42: ...Circuit Operation Description 5 26 Samsung Electronics...
Страница 43: ...Circuit Operation Description Samsung Electronics 5 27...
Страница 44: ...Circuit Operation Description 5 28 Samsung Electronics...
Страница 45: ...Circuit Operation Description Samsung Electronics 5 29...
Страница 46: ...Circuit Operation Description 5 30 Samsung Electronics...
Страница 47: ...Circuit Operation Description Samsung Electronics 5 31 5 3 Logic part 5 3 1 Logic Board Block diagram...
Страница 63: ...Circuit Operation Description Samsung Electronics 5 47 Figure 5 42 Single logic buffer...
Страница 70: ...Circuit Operation Description 5 54 Samsung Electronics...
Страница 71: ...Circuit Operation Description Samsung Electronics 5 55...
Страница 72: ...5 56 Samsung Electronics MEMO...
Страница 73: ...Circuit Operation Description Samsung Electronics 5 57...
Страница 148: ...10 14 Samsung Electronics MEMO...
Страница 158: ...9 10 Samsung Electronics MEMO...
Страница 164: ...3 2 Samsung Electronics MENO...
Страница 170: ...Schematic Diagrams 12 4 Samsung Electronics 12 4 Y Pb Pr Buffer Switching...
Страница 172: ...Schematic Diagrams 12 6 Samsung Electronics 12 6 Deinterlace Progressive Converter TP25 TP26 TP24 TP24 TP25 TP26...
Страница 173: ...Samsung Electronics Schematic Diagrams 12 7 12 7 Analog to Digital Converter...
Страница 174: ...Schematic Diagrams 12 8 Samsung Electronics 12 8 DVI Input Block...
Страница 178: ...Schematic Diagrams 12 12 Samsung Electronics 12 12 Digital Signal Receiver LVDS Transmitter I O expander...
Страница 180: ...Schematic Diagrams 12 14 Samsung Electronics 12 15 Sound AMP Module...
Страница 181: ...Samsung Electronics Schematic Diagrams 12 15 12 16 Component Y Pb Pr Jack Block Sound In Out Block...