Circuit Operation Description
Samsung Electronics
5-9
5-2-1(C) TYPES AND DETAILED EXPLANATION OF DRIVE DISCHARGES
(1 ) Sustaining discharge
Sustaining discharge means a self-sustaining discharge generated by the total of the sustaining pulse
voltage (usually, 160~170V) alternately given to X and Y electrodes during the sustaining period and
the wall voltage that varies depending upon pixels' previous discharge status. It is operated by the
memory function (through this, the current status is defined by previous operation conditions) AC
PDP basically possesses. That is, when there is existing wall voltage in pixels (in other words, when
pixels remain ON), the total of wall voltage and a sustaining voltage to be impressed subsequently
impresses a voltage equal to or above the discharge start voltage, thereby generating discharge again,
but when there is no existing wall voltage in pixels (in other words, when pixels remain OFF), the sus-
taining voltage only does not reach the discharge start voltage, thus causing no discharge. The sustain-
ing discharge is a section generating actual optic outputs used in displaying images.
(2) Address discharge
This means a discharge type generated by the difference between positive voltage of the address elec-
trode (normally 70~75V determined by supplied Va v positive wall charge) and the negative
potential of Y electrode (supplied GND level v negative wall charge). The address discharge
serves to generate wall voltage in pixels where images are to be displayed (that is, discharge is to be
generated) prior to the sustaining discharge section. Namely, pixels with wall voltage by the address
discharge will generate sustaining discharge by the following sustaining pulses.
(3) Erase discharge
The purpose of resetting or erase discharge is to make even wall voltage in all pixels on the panel.
Wall voltage, which may vary depending upon the previous sustaining discharge status, must be
made even. That is, wall voltage generated by the sustaining discharge must surely be removed, by
making discharges and then supplying ions or electrons. Wall voltage can be removed by making dis-
charges and then setting a limitation on time for opposite polarity charging of the wall voltage or gen-
erating weak discharge (Low voltage erasing) to supply an appropriate quantity of ions or electrons
and keep polarities from being charged oppositely. The weak discharge (Low voltage erasing) meth-
ods, which have been known to date, can largely be into two types: 1) the log pulse adopted by most
companies including F Company, and 2) the ramp pulse adopted by Matsushita. In both two methods,
impression is made with a slow rising slope of the erasing pulse. Because the total of the existing wall
voltage and a voltage on the rising pulse must be at least the drive start voltage to generate dis-
charges, external impressed voltage is adjusted based on the difference in wall voltage between pixels.
And, weak discharge is generated because of a small impressed voltage.
Содержание PS42P2SBX/XEC
Страница 2: ...ELECTRONICS Samsung Electronics Co Ltd Nov 2002 Printed in Korea AA82 00157A...
Страница 19: ...Circuit Operation Description Samsung Electronics 5 3 5 1 2 D PDP PS 42 BLOCK DIAGRAM...
Страница 26: ...Circuit Operation Description 5 10 Samsung Electronics 5 2 2 SPECIFICATION OF DRIVE PULSES 5 2 2 A DRIVE PULSES...
Страница 32: ...Circuit Operation Description 5 16 Samsung Electronics 5 2 3 D DRIVER CIRCUIT DIAGRAM...
Страница 33: ...Circuit Operation Description Samsung Electronics 5 17 5 2 3 E DRIVER BOARD CONNECTOR LAYOUT...
Страница 34: ...Circuit Operation Description 5 18 Samsung Electronics...
Страница 35: ...Circuit Operation Description Samsung Electronics 5 19...
Страница 36: ...Circuit Operation Description 5 20 Samsung Electronics...
Страница 37: ...Circuit Operation Description Samsung Electronics 5 21...
Страница 38: ...Circuit Operation Description 5 22 Samsung Electronics...
Страница 39: ...Circuit Operation Description Samsung Electronics 5 23...
Страница 40: ...Circuit Operation Description 5 24 Samsung Electronics...
Страница 41: ...Circuit Operation Description Samsung Electronics 5 25...
Страница 42: ...Circuit Operation Description 5 26 Samsung Electronics...
Страница 43: ...Circuit Operation Description Samsung Electronics 5 27...
Страница 44: ...Circuit Operation Description 5 28 Samsung Electronics...
Страница 45: ...Circuit Operation Description Samsung Electronics 5 29...
Страница 46: ...Circuit Operation Description 5 30 Samsung Electronics...
Страница 47: ...Circuit Operation Description Samsung Electronics 5 31 5 3 Logic part 5 3 1 Logic Board Block diagram...
Страница 63: ...Circuit Operation Description Samsung Electronics 5 47 Figure 5 42 Single logic buffer...
Страница 70: ...Circuit Operation Description 5 54 Samsung Electronics...
Страница 71: ...Circuit Operation Description Samsung Electronics 5 55...
Страница 72: ...5 56 Samsung Electronics MEMO...
Страница 73: ...Circuit Operation Description Samsung Electronics 5 57...
Страница 148: ...10 14 Samsung Electronics MEMO...
Страница 158: ...9 10 Samsung Electronics MEMO...
Страница 164: ...3 2 Samsung Electronics MENO...
Страница 170: ...Schematic Diagrams 12 4 Samsung Electronics 12 4 Y Pb Pr Buffer Switching...
Страница 172: ...Schematic Diagrams 12 6 Samsung Electronics 12 6 Deinterlace Progressive Converter TP25 TP26 TP24 TP24 TP25 TP26...
Страница 173: ...Samsung Electronics Schematic Diagrams 12 7 12 7 Analog to Digital Converter...
Страница 174: ...Schematic Diagrams 12 8 Samsung Electronics 12 8 DVI Input Block...
Страница 178: ...Schematic Diagrams 12 12 Samsung Electronics 12 12 Digital Signal Receiver LVDS Transmitter I O expander...
Страница 180: ...Schematic Diagrams 12 14 Samsung Electronics 12 15 Sound AMP Module...
Страница 181: ...Samsung Electronics Schematic Diagrams 12 15 12 16 Component Y Pb Pr Jack Block Sound In Out Block...