Samsung PS42D5SX/XEC, Руководство по обслуживанию

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Circuit Description
13-12 Samsung Electronics
1. X, Y Control Block
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Drive Circuit Definition
The Drive Circuit is a circuit that generates a waveform (high-voltage pulse) for the X and Y electrode group of the panel's external
port so as to control the panel. The high-voltage switching pulse is generated through the combination of the IC HYBRID (Drive
block + IGBT) and FET.
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Drive Circuit Mechanism
A picture is displayed on the PDP by applying voltage to the X, Y and ADDRESS electrodes of each pixel according to the appro-
priate condition. The drive waveform applied to 42HD V4 is of the ISSS (ISSS: Interweaving Scan and Selective Sustain with Scan
IC) type and has IDS (InDependent Sustain) in the Scan section unlike the existing ADS. Discharges within a PDP pixel can be
classified into 3 types:
①
Address Discharge: To form a wall voltage within the pixel by giving information (applying DATA voltage) to the pixel to be lit.
②
Sustain Discharge: Sustain Discharge is a display section that voluntarily maintains the discharge of the pixels whose wall
voltage has been formed by the Address Discharge. (Optical output for displaying a picture is generated).
③
Erase Discharge: To selectively perform Address Discharge for each pixel, all pixels on the panel should be in the same status
(the wall electric charge status and space electric charge status must be the same). Therefore, the Erase
Discharge section is an important component for guaranteeing the drive margin, and is implemented by
various methods such as applying a log waveform. However, the current 42HD V4 has adopted a wall voltage
control through an RA (Repeated Auto-quenching) reset that separates the discharge area and performs
switching to perform an efficient erase operation, while the gradient was the same in the RAMP section in the
existing approach.
1) Address Discharge
A discharge that is caused by the difference between the plus electric potential (Va apply voltage of 65~70V + Positive Wall
Charge) of the electrode and the negative electric potential (Applied GND Level + Negative Wall Charge) of the Y electrode. The
Address discharge forms a wall voltage within the pixel to display color (to be discharged) before the Sustain Discharge period.
That is, the pixel whose wall charge has been formed by the Address Discharge forms a Sustain Discharge vis the following
Sustain pulse.
2) Sustain Discharge
A Sustain Discharge is a Self-Sustaining Discharge formed by the accumulation of the electric potential of the Sustain pulse (gen-
erally 200 ~ 210 Volt) alternating over the X and Y electrodes during the sustain period, and the wall charge depending on whether
the pixel has previously been discharged or not. That is, it is controlled by the memory characteristics, one of the basic characteris-
tics of the AC PDP (in that the past operating conditions determine the current status). That is, if a wall voltage exists on the pixel
(if the pixel is on), a discharge is formed again because the applied voltage, which is the sum of the following applied Sustain volt-
age and the wall voltage, is higher than the discharge threshold voltage. If no wall voltage exists on the pixel (if the pixel is off), a
discharge will not occur because the Sustain voltage is not higher than the discharge threshold voltage. The Sustain Discharge
period is the period for generating actual optical output so as to display a picture on the PDP screen.
3) Erase Discharge
The purpose of a Reset (Erase) Discharge is to create uniformity of the wall voltage within all panel pixels. It evens the wall volt-
ages regardless of the Sustain Discharge in the previous stage. The Erase Discharge has to remove the wall voltage introduced by
the Sustain Discharge by supplying ions or electrons by a discharge. When the wall voltage is removed through a discharge, the
time when the reverse polarity is applied to the wall voltage (fine width erasing) is to be limited or ions or electrons are to be sup-
plied by a weak discharge (low voltage erasing) so as to prevent a wall charge in reverse polarity.
There are 2 known weak discharge (low-voltage) erase methods. 1) A log waveform adopted by F company and 2) a weak erase
discharge via a ramp waveform adopted by Matsushita and other companies. Both methods control the externally applied voltage
by the difference of the wall voltage of the pixel by applying the rising gradient of the erasing waveform slowly, because the dis-
charge begins when the sum of the existing remaining wall voltage and the rising waveform voltage exceeds the drive threshold
voltage. In addition, a weak discharge is introduced, because the applied voltage is low.