6.
Schematic Diagram
6.14. INTERFACE/SATA BLOCK
S ATA(LOADER)
I2C0_D DC
S ATA(B/E)
BT_DP
BT_DN
DELETE LAYER 2,3,4,5,6 CO P P ER FOR IMP EDANCE
P WM_DATA
2B3<
IPOD_SDA
7E 1<>
7E 1<>
IPOD_SCL
EX3.3V
S DP 1004
IC29
N1
N2
TP 91
TP 92
R9 90
N3
M5
CN99
1002
2
HS
-0
5C
2
.2
K
O
HM
1/16W
1/16W
12F3<>
12F3<>
7E 1<>
12A3<
IPOD_SCL
DRM_S DA
12D4<
8B5>
BEND_SCL
BEND_S DA
8F8<
8F8>
S P I_S IO
R220
R222
AH3
IC29
D3.3V_PW
D3.3V_PW
ST3. 4V
12F3<
D3.3V_PW
D3.3V_B
D3.3V_T
D3.3V_PW
D3.3V_PW
D5.0V_PW
D3.3V_PW
D1.1V_PW
HDMI_RX_AUD_SW
I2C_INT
ADC_RST
AMP_RESET
IPOD_RST
IPOD_VD_S W
GPIO5
I_EXTINT1
HDMI_RX_AUD_SW
P WM_RES ET
GPIO0
AMP_RESET
GPIO7
GPIO4
I_EXTINT1
VARI_P C_B
CKEIN_REQ
DRM_SDA
IPOD_VD_S W
S P I_NSS O
S P I_NSS I
FR ONT_INTB
OTN_INT
I2C_INT
ADC_RST
IPOD_RST
BOOT_MODE
CEC_RX
UART1_RX
CEC_TX
DRM_WP
VARI_P C_A
IPOD_SDA
S P I_CLK
DRM_S CL
S P I_MIO
UART1_T X
P WM_CLK
DRM_SCL
DRM_WP
UART1_T X
UART1_R X
S ATA_TXN
S ATA_RXN
S ATA_TXP
S ATA_RXP
S ATA0_TX-
S
S
S ATA0_RX-
S ATA0_RX-
S ATA0_TX-
S
S
MAIN_S CL
MAIN_S DA
ADC_CLK
ADC_DATA
HU3-_US B
HU3+_US B
S
S ATA0_TX-
S ATA0_RX-
S
SDP1004
A24
A25
A26
A27
AH1
AH2
AH4
AJ5
AJ6
AJ7
AJ11
AJ12
AJ13
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK11
AK12
AK13
AL3
AL4
AL5
AL6
AL7
AL11
AL13
AL14
AM3
AM4
AM5
AM6
AM7
AM8
AM11
AM12
AM13
AM14
B25
B26
B27
C23
C24
C25
C26
C27
D22
D23
D24
D25
D26
D27
UA
XA
TA
QA
33OHM
TI11
33OHM
TI12
33OHM
TI22
33OHM
R279
33OHM
R278
33OHM
R277
CT
S
RT
S
4.7KOHM
R259
4.7KOHM
R-CH IP;4. 7KOHM,5%, 1/16W ,TP ,1005
R257
4.7KOHM
R215
4.7KOHM
TI14
4.7KOHM
TI16
4.7KOHM
TI23
4.7KOHM
TI29
33OHM
R252
8E 8<
8B5<
12B 3<>
12B 3>
12C3>
2.2K
OHM
R299
33OHM
R251
33OHM
R250
33OHM
R240
33OHM
OPTION
R241
33OHM
R246
33OHM
R801
33OHM
R802
33OHM
TI20
33OHM
TI26
33OHM
R803
8F8>
8H6>
47KOHM
OPTION
A
D
R
3
8G5<
5E 5<
7E 4<
9D2<>
8A6>
8F8>
10C8<
2B3<
9C9<
1/16W
2.7KOHM
R943
33OHM
R236
33OHM
R235
33OHM
R244
33OHM
R237
DGND
1/16W
2.7KOHM
R141
OPTIO N
1/16W
0OHM
A
B
R
1
8B5<
12D4>
DGND
2.7KOHM
1/16W
R142
12C3>
12C3<
0OHM
1/16W
A
B
R
2
2E 2<
2E 2<
33OHM
R231
33OHM
R234
33OHM
R230
33OHM
R229
33OHM
R228
33OHM
R227
33OHM
R226
33OHM
R225
33OHM
R224
33OHM
R223
33OHM
33OHM
2C3<
8F8<
12B 3>
12B 3<>
4.7KOHM
R80
4.7KOHM
R82
10D6>
10D6<>
DW
P
_
T
DW
P
_
B
DS
C_
T
DS
C_
B
DS
D_
T
2.2K
OHM
R300
1
/1
6
W
R
3
0
1
DGND
DGND
1
6
V
1
0
0
N
F
C8
0
2
DS
D_
B
M24256-B RMN6TP
IC28
1
2
3
4
5
6
7
8
DGND
DGND_T
DGND_B
1
2
V
OP
TI
ON
L
O
P
IV
A
1
6
G0
5
V
T
9
5
1
2
V
L
O
P
IV
A
1
6
G0
5
OP
TI
ON
V
T
9
6
1
0
K
O
HM
1
/1
6
W
R9
9
9
UA
RT1
_
R
X
UA
RT1
_
T
X
DGND
1
2
3
4
5
DGND
1
0
0
N
F
1
6
V
C9
7
1
1
6
V
1
0
0
N
F
C9
7
2
1
6
V
1
0
0
N
F
C9
7
3
1
6
V
1
0
0
N
F
C9
7
4
1
6
V
1
0
0
N
F
C9
7
5
1
6
V
1
0
0
N
F
C9
7
6
1
6
V
1
0
0
N
F
C9
7
7
DGND
H2
H3
H4
J1
J2
J3
K1
K2
K3
K4
L1
L3
L4
M1
M2
M3
M4
N4
N5
P2
P3
P4
R1
R2
R3
R4
R5
T1
T2
T3
T4
T5
1
6
V
1
0
0
N
F
C9
7
8
10NF
25V
C7 8
10NF 25V
C8 3
10NF
25V
C7 7
25V
10NF
C8 1
0O HM
S AR3
0O HM
S AR4
0O HM
S AR2
0O HM
S AR1
DGND
KT-S A07A-15AKB7-U
OPT ION
CN1
1
2
3
4
5
6
7
12B8<
12D7>
12B8<
12E7>
12D7<
12B8>
12D7<
12B8>
12B8<
12E8>
12E8>
12B8<
12B8>
12E8>
12E8>
12B8>
P CIE_CM
S ATA_CP
S ATA_CM
P CIE_CP
3KOHM
1/16W
R9 89
3KOHM
1/16W
DGND
KT-S A07A-15AKB7-U
OPT ION
CN95
1
2
3
4
5
6
7
DGND
1OHM 1/16W
TI10
1OHM 1/16W
TI9
10E9<
10E9<
1OHM 1/16W
TI6
1OHM 1/16W
TI5
9D3<>
9D3<>
UND
E
FINED
0
.0
1
O
HM
CB2012UA300T
B
D
7
7
CB2012UA300T
0
.0
1
O
HM
UND
E
FINED
B
D
7
8
16V
10NF
C9 79
16V
10NF
C9 81
10NF
16V
C9 80
10NF
16V
C9 82
DGND
RCL
A
M
P
0
5
04F
OP TION
DD2
1
2
3
4
5
6
12E8>
12D7>
12E8>
12D7<
12E8>
12D7<
12E8>
12E7>
DGND
B
T
_
G
B
T
_
D
N
B
T
_
5
V
B
T
_
D
P
UNDEFINED
12507
WS
-H
04G
BCN1
1
2
3
4
MGND1
M
G
N
D
2
i_AY_S ATA1_REFCLKP
i_AY_S ATA1_REFCLKM
i_AY_S ATA0_REFCLKP
i_AY_S ATA0_REFCLKM
i_AY_S ATA1_REFRES
i_AY_S ATA0_REFRES
o_AY_S ATA1_ATES T
o_AY_S ATA0_ATES T
o_AY_S ATA1_TXCLK_DIVN
o_AY_S ATA1_TXCLK_DIVP
i_AY_S ATA1_RXP
i_AY_S ATA1_RXN
o_AY_S ATA1_TXN
o_AY_S ATA1_TXP
o_AY_S ATA0_TXCLK_DIVN
o_AY_S ATA0_TXCLK_DIVP
i_AY_S ATA0_RXP
i_AY_S ATA0_RXN
o_AY_S ATA0_TXN
o_AY_S ATA0_TXP
i_AY_S ATA1_VS S 2
i_AY_S ATA1_VS S 1
p_AY_S ATA1_VS S A2
p_AY_S ATA1_VS S A1
i_AY_S ATA0_VS S 2
i_AY_S ATA0_VS S 1
p_AY_S ATA0_VS S A2
p_AY_S ATA0_VS S A1
p_AY_S ATA1_VDDT
p_AY_S ATA1_VDDHA
p_AY_S ATA1_VDDA
p_AY_S ATA1_VDD
p_AY_S ATA0_VDDT
p_AY_S ATA0_VDDHA
p_AY_S ATA0_VDDA
p_AY_S ATA0_VDD
b_RMI_S IO7
b_RMI_S IO6
b_RMI_S IO5
b_RMI_S IO4
b_RMI_S IO3
b_RMI_S IO2
b_RMI_S IO1
b_RMI_S IO0
o_RMI_RS CK
o_RMI_READY
i_RMI_WVALID
i_RMI_S CK
i_RMI_CEn
b_GP IO0
b_GP IO1
b_GP IO2
b_GP IO3
b_GP IO4
b_GP IO5
b_GP IO6
b_GP IO7
i_EXTINT0
i_EXTINT1
i_EXTINT2
o_S DCARD_CLK
b_S DCARD_CMD
b_S DCARD_DATA0
b_S DCARD_DATA1
b_S DCARD_DATA2
b_S DCARD_DATA3
b_S DCARD_DATA4
b_S DCARD_DATA5
b_S DCARD_DATA6
b_S DCARD_DATA7
i_SD CARD_DET_N
i_SD CARD_WP
i_UART0 _nCTS
o_UART0_nRTS
i_UART0 _RX
o_UART0_TX
i_UART1 _RX
o_UART1_TX
i_UART2 _RX
o_UART2_TX
b_I2C0_CLK
b_I2C0_DATA
b_I2C1_CLK
b_I2C1_DATA
b_I2C2_CLK
b_I2C2_DATA
b_I2C3_CLK
b_I2C3_DATA
o_S P I_CLK
o_S P I_MIO
o_S P I_NS S I
i_SP I_S IO
SDA
VSS
/WC
VCC
SCL
E2
E1
E0
S ATA(LOADER)
I2C0_D DC
S ATA(B/E)
BT_DP
BT_DN
DELETE LAYER 2,3,4,5,6 CO P P ER FOR IMP EDANCE
EX3.
3V
S
DP 1004
1002
2
HS
-0
5C
2
.2
K
O
HM
1/16W
1/16W
D
3.3V_PW
D3.3V_PW
ST3. 4V
D3.3V_PW
D3.3V_PW
D3.3V_PW
D5.0V_PW
D3.3V_PW
D1.1V_PW
SDP1004
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
4.7KOHM
4.7KOHM
R-CH IP;4. 7KOHM,5%, 1/16W ,TP ,1005
4.7KOHM
4.7KOHM
4.7KOHM
4.7KOHM
4.7KOHM
33OHM
2.2K
OHM
33OHM
33OHM
33OHM
33OHM
OPTION
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
47KOHM
OPTION
1/16W
2.7KOHM
33OHM
33OHM
33OHM
33OHM
DGND
1/16W
2.7KOHM
OPTIO N
1/16W
0OHM
DGND
2.7KOHM
1/16W
0OHM
1/16W
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
33OHM
4.7KOHM
4.7KOHM
2.2K
OHM
1
/1
6
W
DGND
DGND
1
6
V
1
0
0
N
F
M24256-B RMN6TP
DGND
1
2
V
OP
TI
ON
L
O
P
IV
A
1
6
G0
5
1
2
V
L
O
P
IV
A
1
6
G0
5
OP
TI
ON
1
0
K
O
HM
1
/1
6
W
DGND
DGND
1
0
0
N
F
1
6
V
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
1
6
V
1
0
0
N
F
DGND
1
6
V
1
0
0
N
F
10NF
25V
10NF 25V
10NF
25V
25V
10NF
0O HM
0O HM
0O HM
0O HM
DGND
KT-S A07A-15AKB7-U
OPT ION
3KOHM
1/16W
3KOHM
1/16W
DGND
KT-S A07A-15AKB7-U
OPT ION
DGND
1OH M 1/1 6W
1OH M 1/1 6W
1OH M 1/1 6W
1OH M 1/1 6W
UND
E
FINED
0
.0
1
O
HM
T
0
0
3
A
U
2
1
0
2
B
C
T
0
0
3
A
U
2
1
0
2
B
C
0
.0
1
O
HM
UND
E
FINED
16V
10NF
16V
10NF
10NF
16V
10NF
16V
DGND
RCL
A
M
P
0
5
04F
OP TION
DGND
UNDEFINED
12507
WS
-H
04G
IC29
TP 91
TP 92
R9 90
CN99
R220
R222
IC29
D3
.3V_B
D3.3V_T
UA
XA
TA
QA
TI11
TI12
TI22
R279
R278
R277
CT
S
RT
S
R259
R257
R215
TI14
TI16
TI23
TI29
R252
R299
R251
R250
R240
R241
R246
R801
R802
TI20
TI26
R803
A
D
R
3
R943
R236
R235
R244
R237
R141
A
B
R
1
R142
A
B
R
2
R231
R234
R230
R229
R228
R227
R226
R225
R224
R223
R80
R82
DW
P
_
T
DW
P
_
B
DS
C_
T
DS
C_
B
DS
D_
T
R300
R3
0
1
C8
0
2
DS
D_
B
IC28
DGND_T
DGND_B
V
T
9
5
V
T
9
6
R9
9
9
UA
RT1
_
R
X
UA
RT1
_
T
X
C9
7
1
C9
7
2
C9
7
3
C9
7
4
C9
7
5
C9
7
6
C9
7
7
C9
7
8
C7 8
C8 3
C7 7
C8 1
S AR3
S AR4
S AR2
S AR1
CN1
P CIE_CM
S ATA_CP
S ATA_CM
P CIE_CP
R9 89
CN95
TI10
TI9
TI6
TI5
B
D
7
7
B
D
7
8
C9 79
C9 81
C9 80
C9 82
DD2
B
T
_
G
B
T
_
D
N
B
T
_
5
V
B
T
_
D
P
BCN1
2B3<
7E 1<>
7E 1<>
12F3<>
12F3<>
7E 1<>
12A3<
12D4<
8B5>
8F8<
8F8>
12F3<
8E 8<
8B5<
12B 3<>
12B 3>
12C3>
8F8>
8H6>
8G5<
5E 5<
7E 4<
9D2<>
8A6>
8F8>
10C8<
2B3<
9C9<
8B5<
12D4>
12C3>
12C3<
2E 2<
2E 2<
2C3<
8F8<
12B 3>
12B 3<>
10D6>
10D6<>
12B8<
12D7>
12B8<
12E7>
12D7<
12B8>
12D7<
12B8>
12E8>
12B8<
12B8>
12E8>
10E9<
10E9<
9D3<>
9D3<>
12E8>
12D7>
12E8> 12D7<
12E8> 12D7<
12E8>
12E7>
P WM_DATA
IPOD_SDA
IPOD_SCL
IPOD_SCL
DRM_S DA
BEND_SCL
BEND_S DA
S P I_S IO
HDMI_RX_AUD_SW
I2C_INT
ADC_RST
AMP_RESET
IPOD_RST
IPOD_VD_S W
GPIO5
I_EXTINT1
HDMI_RX_AUD_SW
P WM_RES ET
GPIO0
AMP_RESET
GPIO7
GPIO4
I_EXTINT1
VARI_P C_B
CKEIN_REQ
DRM_SDA
IPOD_VD_S W
S P I_NSS O
S P I_NSS I
FR ONT_INTB
OTN_INT
I2C_INT
ADC_RST
IPOD_RST
BOOT_MODE
CEC_RX
UART1_RX
CEC_TX
DRM_WP
VARI_P C_A
IPOD_SDA
S P I_CLK
DRM_S CL
S P I_MIO
UART1_T X
P WM_CLK
DRM_SCL
DRM_WP
UART1_T X
UART1_R X
S ATA_TXN
S ATA_RXN
S ATA_TXP
S ATA_RXP
S ATA0_TX-
S
S
S ATA0_RX-
S ATA0_RX-
S ATA0_TX-
S
S
MAIN_S CL
MAIN_S DA
ADC_CLK
ADC_DATA
HU3-_US B
HU3+_US B
S
S ATA0_TX-
S ATA0_RX-
S
N1
N2
N3
M5
AH3
A24
A25
A26
A27
AH1
AH2
AH4
AJ5
AJ6
AJ7
AJ11
AJ12
AJ13
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK11
AK12
AK13
AL3
AL4
AL5
AL6
AL7
AL11
AL13
AL14
AM3
AM4
AM5
AM6
AM7
AM8
AM11
AM12
AM13
AM14
B25
B26
B27
C23
C24
C25
C26
C27
D22
D23
D24
D25
D26
D27
1
2
3
4
5
6
7
8
1
2
3
4
5
H2
H3
H4
J1
J2
J3
K1
K2
K3
K4
L1
L3
L4
M1
M2
M3
M4
N4
N5
P2
P3
P4
R1
R2
R3
R4
R5
T1
T2
T3
T4
T5
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
2
3
4
5
6
1
2
3
4
MGND1
M
G
N
D
2
i_AY_S ATA1_REFCLKP
i_AY_S ATA1_REFCLKM
i_AY_S ATA0_REFCLKP
i_AY_S ATA0_REFCLKM
i_AY_S ATA1_REFRES
i_AY_S ATA0_REFRES
o_AY_S ATA1_ATES T
o_AY_S ATA0_ATES T
o_AY_S ATA1_TXCLK_DIVN
o_AY_S ATA1_TXCLK_DIVP
i_AY_S ATA1_RXP
i_AY_S ATA1_RXN
o_AY_S ATA1_TXN
o_AY_S ATA1_TXP
o_AY_S ATA0_TXCLK_DIVN
o_AY_S ATA0_TXCLK_DIVP
i_AY_S ATA0_RXP
i_AY_S ATA0_RXN
o_AY_S ATA0_TXN
o_AY_S ATA0_TXP
i_AY_S ATA1_VS S 2
i_AY_S ATA1_VS S 1
p_AY_S ATA1_VS S A2
p_AY_S ATA1_VS S A1
i_AY_S ATA0_VS S 2
i_AY_S ATA0_VS S 1
p_AY_S ATA0_VS S A2
p_AY_S ATA0_VS S A1
p_AY_S ATA1_VDDT
p_AY_S ATA1_VDDHA
p_AY_S ATA1_VDDA
p_AY_S ATA1_VDD
p_AY_S ATA0_VDDT
p_AY_S ATA0_VDDHA
p_AY_S ATA0_VDDA
p_AY_S ATA0_VDD
b_RMI_S IO7
b_RMI_S IO6
b_RMI_S IO5
b_RMI_S IO4
b_RMI_S IO3
b_RMI_S IO2
b_RMI_S IO1
b_RMI_S IO0
o_RMI_RS CK
o_RMI_READY
i_RMI_WVALID
i_RMI_S CK
i_RMI_CEn
b_GP IO0
b_GP IO1
b_GP IO2
b_GP IO3
b_GP IO4
b_GP IO5
b_GP IO6
b_GP IO7
i_EXTINT0
i_EXTINT1
i_EXTINT2
o_S DCARD_CLK
b_S DCARD_CMD
b_S DCARD_DATA0
b_S DCARD_DATA1
b_S DCARD_DATA2
b_S DCARD_DATA3
b_S DCARD_DATA4
b_S DCARD_DATA5
b_S DCARD_DATA6
b_S DCARD_DATA7
i_SD CARD_DET_N
i_SD CARD_WP
i_UART0 _nCTS
o_UART0_nRTS
i_UART0 _RX
o_UART0_TX
i_UART1 _RX
o_UART1_TX
i_UART2 _RX
o_UART2_TX
b_I2C0_CLK
b_I2C0_DATA
b_I2C1_CLK
b_I2C1_DATA
b_I2C2_CLK
b_I2C2_DATA
b_I2C3_CLK
b_I2C3_DATA
o_S P I_CLK
o_S P I_MIO
o_S P I_NS S I
i_SP I_S IO
S DA
VS S
/WC
VCC
S CL
E2
E1
E0
P
OWER
Copyright© 1995-2012 SAMSUNG. All rights reserved.
6-17
Содержание HT-E6730W
Страница 62: ...5 PCB Diagram 5 2 FRONT PCB Top CN1 1 TP2 5 2 Copyright 1995 2012 SAMSUNG All rights reserved ...
Страница 64: ...5 PCB Diagram 5 2 2 Test Point Wave Form TP2 5 4 Copyright 1995 2012 SAMSUNG All rights reserved ...
Страница 65: ...5 PCB Diagram 5 3 FRONT PCB Bottom CN5 IC 1 CN1 0 IC2 Copyright 1995 2012 SAMSUNG All rights reserved 5 5 ...
Страница 69: ...5 PCB Diagram 5 4 2 Test Point Wave Form TP3 TP4 TP5 Copyright 1995 2012 SAMSUNG All rights reserved 5 9 ...
Страница 73: ...5 PCB Diagram 5 7 USB PCB Bottom Copyright 1995 2012 SAMSUNG All rights reserved 5 13 ...
Страница 74: ...5 PCB Diagram 5 8 VT PCB Top VCN3 VCN4 VCN5 1 5 14 Copyright 1995 2012 SAMSUNG All rights reserved ...
Страница 76: ...5 PCB Diagram 5 9 VT PCB Bottom 5 16 Copyright 1995 2012 SAMSUNG All rights reserved ...
Страница 79: ...5 PCB Diagram 5 10 2 Test Point Wave Form TP1 Copyright 1995 2012 SAMSUNG All rights reserved 5 19 ...
Страница 80: ...5 PCB Diagram 5 11 SMPS PCB Bottom 5 20 Copyright 1995 2012 SAMSUNG All rights reserved ...
Страница 83: ...6 Schematic Diagram 6 2 1 Test Point Wave Form TP2 Copyright 1995 2012 SAMSUNG All rights reserved 6 3 ...
Страница 89: ...6 Schematic Diagram 6 7 1 Test Point Wave Form TP5 Copyright 1995 2012 SAMSUNG All rights reserved 6 9 ...
Страница 95: ...6 Schematic Diagram 6 12 1 Test Point Wave Form TP3 TP4 Copyright 1995 2012 SAMSUNG All rights reserved 6 15 ...
Страница 99: ...6 Schematic Diagram 6 16 FIRENCE POWER JTAG DEBUG Copyright 1995 2012 SAMSUNG All rights reserved 6 19 ...
Страница 105: ...6 Schematic Diagram 6 21 1 Test Point Wave Form TP1 Copyright 1995 2012 SAMSUNG All rights reserved 6 25 ...