Circuit Operating Descriptions
7-17
Speed error detection
HSW
generation
Phase error detection
Digital filter
Digital filter
PWM
conversion
Digital filter
Bias value addition
RECCTL generation
Phase detection
Digital filter
Speed error detection
PBCTL amplifier
RECCTL head
Kp
Kp
Kv
Kv
(Drum speed gain)
(Drum phase gain)
(Capstan phase gain)
CFG amplifier
VSYNC separation
circuit
composite sync
signal
Vertical sync signal
DPG comparator
DFG amplifier
PWM
conversion
Motor driver
Motor driver
Carrier rejection filter
Carrier rejection filter
M
Drum motor
M
Capstan motor
CFG signal
DPG signal
DFG signal
Remark The broken line indicates the internal processing of the MICOM
Fig. 7-18 Block Diagram
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