COMMAND RANGING & TELEMETRY UNIT CORTEX
Is.Rev.
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3.3.16.
Descrambling mode (LFSR polynomials)
3.3.16.1.
General
The current descrambling used in the Cortex CRT is a LFSR one with CCSDS parameters.
In order to support other configurations, we implemented the possibility to change the descrambling LFSR
polynomial, the register initialization and the scrambling mode.
This new feature is available with a license (defined in TMU registry) in the newest version of the software (6.17
and more)
3.3.16.2.
CCSDS Descrambling
Here’s the example for CCSDS descrambling:
𝐻 = 𝑥
8
+ +𝑥
7
+ 𝑥
5
+ 𝑥
3
+ 1
Init registers = ‘1’
Figure 49: CCSDS descrambling
3.3.16.3.
Configuration of the Descrambling
The descrambling in the Cortex CRT will now be able to use a polynomial with a degree up to 31.
The registers init will also be available for all 32 registers.
A third parameter will allow the user to set an offset in order to start the descrambling a few bits after the sync
word.
Note that for CCSDS mode and After and/or Before mode, the descrambling will always restart the PN sequence
when hitting the sync word. The sync word is still not descrambled.