rtd DM34216HR, Руководство пользователя

Страница: 45 / 76

RTD Embedded Technologies, Inc.
| www.rtd.com
45 DM34216HR
User’s Manual
BDM-610010056 Rev A
6.5.2 M
ODE
_S
TATUS
(R
EAD
/W
RITE
, R
EAD
-O
NLY
)
Selects the current mode of operation and indicates its triggering status.
B[3:0]: Mode
o
0x04: Uninitialized. This is the power-on state. No converter initialization has taken place. Sampling is stopped, and all
counters are reset and the triggering state machine is reset. Transition to any of the other Modes will start converter
initialization (sampling will not start until initialization is complete).
o
0x00: Reset. Sampling is stopped. All counters are reset and the triggering state machine is reset.
o
0x01: Paused. Sampling is stopped, but the counters and triggering state machine maintain their state.
o
0x02: Go, Single-Shot. After filling the buffer with the Post-Stop samples, capturing stops. The Mode must be set back
to RESET in order to capture more samples.
o
0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine
is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger.
B[7:4]: Status
o
0x08: Uninitialized – The status when in the “Uninitialized” mode and the converter requires initialization.
o
0x09: Initializing
o
0x00: Stopped – The status when i n the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01: Filling Pre-Trigger buffer
o
0x02: Waiting for start trigger
o
0x03: Sampling/Waiting for stop trigger
o
0x04: Filling Post-Stop buffer
o
0x05: Wait to re-arm – Waiting until local FIFO is empty so the pre-trigger buffer can be filled.
o
0x07: Done capturing
6.5.3 CLK_SRC (R
EAD
/W
RITE
)
Selects the source for the clock of this function block.
o
0x00: System clock/immediate
o
0x01: Never
o
0x02: CLK_BUS2
o
0x03: CLK_BUS3
o
0x04: CLK_BUS4
o
0x05: CLK_BUS5
o
0x06: CLK_BUS6
o
0x07: CLK_BUS7
o
0x08: Advanced Interrupt
o
0x09: Reserved
o
0x0A: CLK_BUS2 Inverted
o
0x0B: CLK_BUS3 Inverted
o
0x0C: CLK_BUS4 Inverted
o
0x0D: CLK_BUS5 Inverted
o
0x0E: CLK_BUS6 Inverted
o
0x0F: CLK_BUS7 Inverted
6.5.4 START_TRIG (R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger, unless PRE_START_COUNT is non-zero in
which case CLK_DIV will start counting immediately.
Refer to CLK_SRC (Read/Write) section above, for list of valid values.