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58
DM34216HR
User’s Manual
BDM-610010056 Rev A
6.3
BAR2: External Clocking
This function block provides interface to the Incremental Encoder function block.
6.3.1
F
UNCTION
B
LOCK
R
EGISTER
M
AP
Table 19:External Clocking Functional Block
Offset
0x03
0x02
0x01
0x00
H
ea
de
r FB + 0x00
FB_ID
FB + 0x04
FB_DMA_BUFFERS
FB_DMA_CHANNELS
Reserved
Reserved
FB + 0x08
EXT_CLK_EDGE
EXT_CLK_DIR
EXT_CLK_GATE_IN
EXT_CLK_IN
FB + 0x0C
EXT_CLK2_PW
FB + 0x10
EXT_CLK3_PW
FB + 0x14
EXT_CLK4_PW
FB + 0x18
EXT_CLK5_PW
FB + 0x1C
EXT_CLK6_PW
FB + 0x20
EXT_CLK7_PW
FB + 0x24
EXT_CLK3_CFG
EXT_CLK2_CFG
Reserved
Reserved
FB + 0x28
EXT_CLK7_CFG
EXT_CLK6_CFG
EXT_CLK5_CFG
EXT_CLK4_CFG
6.3.2
EXT_CLK_IN
(R
EAD
-O
NLY
)
This register provides the current value on the External Clocking lines. The bits in the register correspond with the External Clocking pins as
follows:
Bit CN3 Pin # CLK_BUS
Signal
5
11
7
EXT_CLK_7
4
9
6
EXT_CLK_6
3
7
5
EXT_CLK_5
2
5
4
EXT_CLK_4
1
3
3
EXT_CLK_3
0
1
2
EXT_CLK_2
6.3.3
EXT_CLK_GATE_IN
(R
EAD
O
NLY
)
This register provides the current value on the External Clocking Gates lines. External Clocking Gates can only be used when inputting an
external clock. The bits in the register correspond with the External Clocking Gates pins as follows:
Bit CN3 Pin # CLK_BUS
Signal
5
12
7
EXT_CLK_GATE7
4
10
6
EXT_CLK_GATE6
3
8
5
EXT_CLK_GATE5
2
6
4
EXT_CLK_GATE4
1
4
3
EXT_CLK_GATE3
0
2
2
EXT_CLK_GATE2
6.3.4
EXT_CLK_DIR
(R
EAD
/W
RITE
)
Selects the direction of the External Clocking bits. 0=input, 1=output.
All pins default to inputs at power-up.
6.3.5
EXT_CLK_EDGE
(R
EAD
/W
RITE
)
Selects which edge detect to trigger on. This is a bit settable register.
0= Rising Edge Detect, 1= Fall Edge Detect.