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39
DM34216HR
User’s Manual
BDM-610010056 Rev A
B[7:4]: Status
o
0x08: Uninitialized
–
The status when in the “Uninitialized” mode and the converter requires initialization.
o
0x09: Initializing
o
0x00: Stopped
–
The status when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01: Filling Pre-Trigger buffer
o
0x02: Waiting for start trigger
o
0x03: Sampling/Waiting for stop trigger
o
0x04: Filling Post-Stop buffer
o
0x05: Wait to re-arm
–
Waiting until local FIFO is empty, so the pre-trigger buffer can be filled.
o
0x07: Done capturing
6.4.3
START_TRIG
(R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. The ADC will start capturing after the start trigger, unless PRE_TRIGGER_CAPTURE is non-zero
in which case the ADC will start capturing immediately.
Below is the list of clock sources and the register value needed to select the source.
B[7:0]:
o
0x00: System clock/immediate
o
0x01: Never
o
0x02: CLK_BUS2
o
0x03: CLK_BUS3
o
0x04: CLK_BUS4
o
0x05: CLK_BUS5
o
0x06: CLK_BUS6
o
0x07: CLK_BUS7
o
0x08: Threshold
–
ADC has exceeded the High or Low threshold.
o
0x09: Threshold Inverted
–
The ADC is within the High and Low threshold.
o
0x0A: CLK_BUS2 Inverted
o
0x0B: CLK_BUS3 Inverted
o
0x0C: CLK_BUS4 Inverted
o
0x0D: CLK_BUS5 Inverted
o
0x0E: CLK_BUS6 Inverted
o
0x0F: CLK_BUS7 Inverted
6.4.4
STOP_TRIG
(R
EAD
/W
RITE
)
Selects the stop trigger from the clock bus.
Refer to
section above, or list of valid values.
6.4.5
CLK_DIV(R
EAD
/W
RITE
)
Divider for the sample clock.
𝑆𝑎𝑚𝑝𝑙𝑒 𝐶𝑙𝑜𝑐𝑘 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 =
200 𝑀𝐻𝑧
(2 × 𝐶𝐿𝐾_𝐷𝐼𝑉)
Maximum clock rate is 25Mhz, CLK_DIV = 0x04
Minimum clock rate is 1Mhz, CLK_DIV = 0x64
Disabling clock, CLK_DIV = 0x00
6.4.6
CLK_DELAY(R
EAD
/W
RITE
)
This register is u
sed to set a delay relative to the ADC’s distribution clock. This delay will only be noticeable affect the ADC output clocks
have
been synchronized by using the …. register of the Clock Generator function block.
