CMX47786HX
RTD Embedded Technologies, Inc.
47
DACKx*
O
DMA ACKnowledge x=0-7, active low, used to acknowledge DMA re-
quests.
DRQx
I
DMA Request x=0-7: these are asynchronous lines used by peripheral
devices to request DMA service. They have increasing priority from
DRQ0 up to DRQ7. A DMA request is performed by setting the DRQ
line high and keeping it high until the corresponding DACK line is ac-
tivated.
ENDXFR*
I/O
This is the only synchronous signal of the PC/104 bus and it is active
low. It indicates that the current bus cycle must be performed with 0
wait states. It is used only for 16-bit boards.
IOCHCHK*
I
I/O Channel Check, active low, indicates an error condition that cannot
be corrected.
IOCHRDY
I
I/O Channel Ready: this line, usually high (ready) is pulled to a low lev-
el by devices which need longer bus cycles.
IOCS16*
I
I/O Chip Select 16-bit: this line, active low, is controlled by devices
mapped in the I/O address space. It indicates they have a 16-bit bus
width.
IOR*
O
I/O Read, active low, indicates when the devices present on the bus can
send their information on the data bus.
IOW*
O
I/O Write, active low. When active, it allows the peripheral devices to
read data present on the data bus.
IRQx
I
Interrupt Request: x = 2 to 15, active on rising edge. IRQ15 has top pri-
ority; the other lines have decreasing priority starting from IRQ14 down
to IRQ2. An interrupt request is performed by changing the level of the
corresponding line from low to high and keeping it high until the micro-
processor has recognized it.
KEY
N/A
These locations contain mechanical keying pins to help prevent incor-
rect connector insertion.
LA23-LA17
O
These signals select a 128kbyte window in the 16Mbyte address space
available on the bus.
MASTER*
I
During a DMA cycle, this active-low signal, indicates that a resource on
the bus is about to drive the data and address lines.
MEMCS16*
I
Memory Chip Select 16-bit: this line, active low, is controlled by devic-
es mapped in the memory address space and indicates they have a 16-
bit bus width.
MEMR*
I/O
This active-low signal indicates a memory read operation. Devices us-
ing this signal must decode the address on lines LA23-LA17 and SA19-
SA0.
MEMW*
I/O
This active-low signal indicates a memory write operation. Devices us-
ing this signal must decode the address on lines LA23-LA17 and SA19-
SA0.
OSC
O
OSCillator: clock with a 70 ns period and a 50% duty cycle. It is a
14.31818 MHz always presents.
REFRESH*
I
This cpuModule does not support refresh on the ISA bus. This pin is
pulled high with a 4.7 K ohm resistor and may be driven by another card
in the PC/104 stack. This line is active low and indicates that the current
bus cycle is a DRAM refresh cycle. The refresh cycles are activated ev-
ery 15 microseconds.
Table 26: PC/104 Bus Signals
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