rtd CM17202, Руководство пользователя

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CM17202 Fast Ethernet Controller utilityModule
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8 RTD Embedded Technologies, Inc.
PC/104-Plus PCI Bus Signals
The following table contains brief descriptions of the PC/104-Plus PCI bus signals.
Address and Data
AD[31:00] -- Address and Data are multiplexed. A bus transaction consists of an address cycle followed by one
or more data cycles.
C/BE[3:0]* -- Bus Command/Byte Enables are multiplexed. During the address cycle, the command is defined.
During the Data cycle, they define the byte enables.
PAR -- Parity is even on AD[31:00] and C/BE[3:0]* and is required.
Interface Control Pins
FRAME* -- Frame is driven by the current master to indicate the start of a transaction and will remain active
until the final data cycle.
TRDY* -- Target Ready indicates the selected devices ability to complete the current data cycle of the
transaction. Both IRDY* and TRDY* must be asserted to terminate a data cycle.
IRDY* -- Initiator Ready indicates the master's ability to complete the current data cycle of the transaction.
STOP* -- Stop indicates the current selected device is requesting the master to stop the current transaction.
DEVSEL* -- Device Select is driven by the target device when its address is decoded.
IDSEL -- Initialization Device Select is used as a chip-select during configuration.
LOCK* -- Lock indicates an operation that may require multiple transactions to complete.
Error Reporting
PERR* -- Parity Error is for reporting data parity errors.
SERR* -- System Error is for reporting address parity errors.
Arbitration (Bus Masters Only)
REQ* -- Request indicates to the arbitrator that this device desires use of the bus.
GNT* -- Grant indicates to the requesting device that access has been granted.
System
CLK -- Clock provides timing for all transactions on the PCI bus.
RST* -- Reset is used to bring PCI-specific registers to a known state.