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± 2g / 4g / 8g / 16g Tri-axis Digital

Accelerometer Technical

Reference Manual

PART NUMBER:

KX132-1211

Rev. 1.0

31-Jul-2019

36 Thornwood Dr.

–

Ithaca, NY 14850

© 2019 Kionix

–

All Rights Reserved

tel: 607-257-1080 – fax:607-257-1146

893-12874-1907311402-0.17

www.kionix.com -

[email protected]

Page

19

of

73

CNTL2

Control register 2. Read/write control register that primarily controls tilt position state enabling. This register has also
settings to verify proper power up. This register is On-The-Fly (OTF) register and can be written to while the KX132-
1211

is enabled (PC1 bit in CNTL1 register is set to “1”) and the change will be accepted with no interruption in the

operation. The exception is the SRST bit 7. To change the value of the SRST bit, the PC1 bit in CNTL1 register must
first be set to 0.

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

SRST

COTC

LEM

RIM

DOM

UPM

FDM

FUM

Reset Value

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00111111

Address:

0x1C

SRST

– The Software Reset bit initiates software reset, which performs the RAM reboot routine. This

bit will remain 1 until the RAM reboot routine is finished. Please refer to Technical Note

Power-On Procedure

for more information on software reset.

SRST = 0

– no action

SRST = 1

– start POR / RAM reboot routine

Note 1: For I

2

C Communication: Setting SRST = 1 will NOT result in an ACK, since the part

immediately enters the RAM reboot routine. NACK may be used to confirm this command.

Note 2: To change the value of the SRST bit, the PC1 bit in CNTL1 register must first be set
to 0.

COTC

– The Command Test Control bit is used to verify proper ASIC functionality.

COTC = 0

– no action

COTC = 1

– sets COTR register to 0xAA. When COTR register is then read, sets COTC bit to

0 and sets COTR register to 0x55.

LEM, RIM, DOM, UPM, FDM, FUM

– these bits control the tilt axis mask. Per Table 8, if a direction’s

bit is set to one (1), tilt in that direction will generate an interrupt. If it is set to zero (0), tilt in that
direction will not generate an interrupt.

Bit

Description

LEM

Left state enable

(X-)

RIM

Right state enable

(X+)

DOM

Down state enable

(Y-)

UPM

Up state enable

(Y+)

FDM

Face-Down state enable

(Z-)

FUM

Face-Up state enable

(Z+)

Table 8:

Tilt Direction

TM

Axis Mask

«
...
17
18
19
20
21
...
»

Содержание Kionix KX132-1211

Страница 1: ...A ROHM Group Company KX132 1211 Rev 1 0 31 Jul 2019 Kionix Inc 36 Thornwood Drive Ithaca NY 14850 USA TEL 1 607 257 1800 http www kionix com info kionix com TECHNICAL REFERENCE MANUAL...

Страница 2: ...hts Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 2 of 73 Overview This technical reference manual contains information for KX132 1211 Explan...

Страница 3: ...UT REGISTERS 0X02 0X07 8 XADP_L 8 XADP_H 8 YADP_L 8 YADP_H 8 ZADP_L 9 ZADP_H 9 1 5 ACCELEROMETER OUTPUT REGISTERS 0X08 0X0D 10 XOUT_L 11 XOUT_H 11 YOUT_L 11 YOUT_H 11 ZOUT_L 12 ZOUT_H 12 1 6 COTR 0X12...

Страница 4: ...39 1 20 LP_CNTL2 0X3B 39 1 21 WAKE UP BACK TO SLEEP THRESHOLD AND COUNTER SETUP REGISTERS 0X49 0X4D 40 WUFTH BTSWUFTH BTSTH 40 BTSC 40 WUFC 40 1 22 SELF_TEST 0X5D 41 1 23 OUTPUT BUFFER REGISTERS 0X5E...

Страница 5: ...ce Counter 52 Pulse Reject Mode 52 Integration with Advanced Data Path ADP 52 Threshold Resolution 53 Threshold Calculation 53 Relative Absolute Threshold Modes Select 53 Examples 56 2 3 DIRECTIONAL T...

Страница 6: ...ET2 R W 06 ZADP_L R 21 ODCNTL1 R W 3A LP_CNTL11 R W 07 ZADP_H R 22 INC11 R W 3B LP_CNTL21 R W 08 XOUT_L R 23 INC21 R W 3C 48 Kionix Reserved3 09 XOUT_H R 24 INC31 R W 49 WUFTH2 R W 0A YOUT_L R 25 INC4...

Страница 7: ...I codes 0x4B 0x69 0x6F 0x6E R R R R R R R R MANID7 MANID6 MANID5 MANID4 MANID3 MANID2 MANID1 MANID0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address 0x00 1 3 PART_ID 0x01 A burst read reading using the...

Страница 8: ...bits in ADP_CNTL1 register The output data is provided in 2 s complement data format and is protected while reading using auto increment mode XADP_L X axis Advanced Data Path ADP output least signific...

Страница 9: ...74 1907311402 0 17 www kionix com info kionix com Page 9 of 73 ZADP_L Z axis Advanced Data Path ADP output least significant byte R R R R R R R R ZHP7 ZHP6 ZHP5 ZHP4 ZHP3 ZHP2 ZHP1 ZHP0 Bit7 Bit6 Bit5...

Страница 10: ...counts to acceleration g per Table 2 below For example if N 16 bits then the Counts range is from 32768 to 32767 and if N 8 bits then the Counts range is from 128 to 127 16 bit Register Data 2 s comp...

Страница 11: ...T1 XOUT0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address 0x08 XOUT_H X axis accelerometer output most significant byte R R R R R R R R XOUT15 XOUT14 XOUT13 XOUT12 XOUT11 XOUT10 XOUT9 XOUT8 Bit7 Bit6 B...

Страница 12: ...x0D 1 6 COTR 0X12 The Command Test Response COTR register is used to verify proper integrated circuit functionality The value of this register will change from a default value of 0x55 to 0xAA when COT...

Страница 13: ...at the user defined ODR frequency determined by OTP 1 0 in CNTL3 Data is protected during register read Table 3 describes the reported position for each bit value TSCP Current Tilt Position Register R...

Страница 14: ...elease register INT_REL is read R R R R R R R R Reserved Reserved TLE TRI TDO TUP TFD TFU Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address 0x16 Bit Description TLE X Negative X Reported TRI X Positive...

Страница 15: ...ark WMI 0 Buffer watermark has not been exceeded WMI 1 Buffer watermark has been exceeded DRDY Data Ready DRDY interrupt bit indicates that new acceleration data is available in output data registers...

Страница 16: ...t4 Bit3 Bit2 Bit1 Bit0 Address 0x18 WUFS Wake up interrupt This bit is cleared when the interrupt latch release register INT_REL is read WUFS 1 Motion is above wake up threshold WUFS 0 Motion is below...

Страница 17: ...urred WAKE reports the wake back to sleep state 0 back to sleep state 1 wake state Note Wake is the default state at power up shown in STATUS_REG register For wake engine only operation set MAN_SLEEP...

Страница 18: ...h Performance or Low Power mode RES The RES bit determines the performance mode of the KX132 1211 The noise varies with ODR RES and different LP_CNTL1 settings possibly reducing the effective resoluti...

Страница 19: ...which performs the RAM reboot routine This bit will remain 1 until the RAM reboot routine is finished Please refer to Technical Note TN027 Power On Procedure for more information on software reset SRS...

Страница 20: ...ault Tilt Position ODR is 12 5Hz OTP1 OTP0 Output Data Rate Hz 0 0 1 563 0 1 6 25 1 0 12 5 1 1 50 Table 9 Tilt Position Function Output Data Rate OTDT 2 0 ODR Tap Double TapTM OTDT sets the output dat...

Страница 21: ...r Ithaca NY 14850 2019 Kionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 21 of 73 OWUF2 OWUF1 OWUF0 Output Data Rate Hz 0 0 0 0...

Страница 22: ...Engine enable bit WUFE 0 Wake Up Function Engine is disabled WUFE 1 Wake Up Function Engine is enabled BTSE Back to Sleep Engine enable bit BTSE 0 Back to Sleep Engine is disabled BTSE 1 Back to Sleep...

Страница 23: ...Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x1F ADPE Advanced Data Path ADP enable ADPE 0 Advanced Data Path is disabled ADPE 1 Advanced Data Path is enabled Outputs are available in XADP YA...

Страница 24: ...e change will be accepted with no interruption in the operation R W R W R W R W R W R W R W R W I2C_ALE Reserved Reserved Reserved Reserved Reserved I2C_ALC1 I2C_ALC0 Reset Value Bit7 Bit6 Bit5 Bit4 B...

Страница 25: ...W R W R W R W IIR_BYPASS LPRO FSTUP Reserved OSA3 OSA2 OSA1 OSA0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000110 Address 0x21 IIR_BYPASS IIR Filter Bypass mode enable bit IIR_BYPASS 0 IIR...

Страница 26: ...me in High Performance mode would be fixed See KX132 1211 Product specifications for details FSTUP 0 Fast Start is disabled FSTUP 1 Fast Start is enabled Reserved this bit is reserved and its value sh...

Страница 27: ...s 0x22 PW1 1 0 Pulse INT1 pin width configuration 00 50 sec 10 sec if accelerometer ODR OSA 3 0 1600Hz 01 1 OSA period 10 2 OSA periods 11 Real time mode When PW1 0 Interrupt source auto clearing ACLR...

Страница 28: ...anged AOI AND OR configuration on motion detection AOI 0 OR combination between selected directions AOI 1 AND combination between selected axes Ex If all directions are enabled Active state in OR conf...

Страница 29: ...R W R W R W 0 TMEN TLEM TRIM TDOM TUPM TFDM TFUM Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00111111 Address 0x24 TMEN enables disables alternate tap masking scheme TMEN 0 alternate tap maski...

Страница 30: ...errupt reported on physical interrupt pin INT1 BFI 0 disable BFI 1 enable WMI1 Watermark interrupt reported on physical interrupt pin INT1 WMI1 0 disable WMI1 1 enable Note WMI BFI1 are level triggere...

Страница 31: ...should be set to keep consistency between the internal status and the physical interrupt IEN2 enables disables the physical interrupt pin IEN2 0 physical interrupt pin is disabled IEN2 1 physical inte...

Страница 32: ...interrupt reported on physical interrupt pin INT2 BF2 0 disable BF2 1 enable WMI2 Watermark interrupt reported on physical interrupt pin INT2 WMI2 0 disable WMI2 1 enable Note WMI is a level triggered...

Страница 33: ...Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x29 1 16 TAP DOUBLE TAP CONTROL REGISTERS 0x2A 0x31 The TapTM Double TapTM engine is enabled with TDTE bit in CNTL1 register and can be config...

Страница 34: ...of the 4g output value independent of the actual g range setting of the device Though this is an 8 bit register the register value is internally multiplied by two to set the high threshold This multip...

Страница 35: ...y count is calculated as 2 ODR delay period When the Directional TapTM ODR is 1600Hz every count is calculated as 4 ODR delay period The Directional TapTM ODR is user defined per Table 10 To ensure th...

Страница 36: ...S 0x32 0x34 The Free fall engine is enabled with FFIE bit in FFCNTL register and can be configured via control registers 0x32 0x34 Please refer to Free fall Detect section for detailed information on...

Страница 37: ...IE ULMODE FFDC1 FFDC0 DCRM OFFI2 OFFI1 OFFI0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x34 FFIE Free fall engine enable FFIE 0 disable FFIE 1 enable ULMODE Free fall interr...

Страница 38: ...ngs LINK R W R W R W R W R W R W R W R W LL7 LL6 LL5 LL4 LL3 LL2 LL1 LL0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00001100 Address 0x37 TILT_ANGLE_HL Tilt Angle High Limit This register set...

Страница 39: ...1000011 Address 0x3A AVC 2 0 Averaging Filter Control 000 No Averaging requires IIR_BYPASS 0 setting in ODCNTL register 001 2 Samples Averaged 010 4 Samples Averaged 011 8 Samples Averaged 100 16 Samp...

Страница 40: ...or details on how to configure these registers R W R W R W R W R W R W R W R W Address Register Reset Value WUFTH7 WUFTH6 WUFTH5 WUFTH4 WUFTH3 WUFTH2 WUFTH1 WUFTH0 0x49 WUFTH 10000000 0 BTSTH10 BTSTH9...

Страница 41: ...to enable the MEMS self test function Once the self test function is enabled electrostatic actuation of the accelerometer results in a DC shift of the X Y and Z axis outputs Calculate the self test S...

Страница 42: ...R W R W R W R W R W SMP_TH7 SMP_TH6 SMP_TH5 SMP_TH4 SMP_TH3 SMP_TH2 SMP_TH1 SMP_TH0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x5E SMP_TH 7 0 Sample Threshold determines th...

Страница 43: ...ndby mode Note 2 Additional control of data to be buffered is available via ADP_BUF_SEL bit7 in ADP_CNTL2 register BRES determines the resolution of the acceleration data samples collected by the samp...

Страница 44: ...re sample buffer are cleared when any data is written to this register This causes the sample level bits SMP_LEV 9 0 to be cleared in BUF_STATUS_1 and BUF_STATUS_2 registers In addition if the sample...

Страница 45: ...Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x64 Reserved this bit is reserved and its value should not be changed RMS_AVC 2 0 Number of samples used to calculate RMS output Each sample...

Страница 46: ...Back to Sleep engines ADP_WB_ISEL 0 Accelerometer data is selected ADP data is bypassed ADP_WB_ISEL 1 ADP data is selected Note ODR for the Wake up Back to Sleep would be set but OADP 3 0 and not by O...

Страница 47: ...ficient 1 A ADP_CNTL4 ADP_CNTL5 ADP_CNTL6 Advanced Data Path ADP Control registers 4 5 and 6 R W R W R W R W R W R W R W R W ADP_CNTL4 ADP_F1_BA7 ADP_F1_BA6 ADP_F1_BA5 ADP_F1_BA4 ADP_F1_BA3 ADP_F1_BA2...

Страница 48: ...Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x6B R W R W R W R W R W R W R W R W ADP_CNTL9 0 ADP_F1_CA22 ADP_F1_CA21 ADP_F1_CA20 ADP_F1_CA19 ADP_F1_CA18 ADP_F1_CA17 ADP_F1_CA16 Reset Value Bi...

Страница 49: ...it4 Bit3 Bit2 Bit1 Bit0 00000000 Address 0x70 ADP_F2_BA 14 0 ADP filter 2 coefficient B A ADP_CNTL14 ADP_CNTL15 ADP_CNTL16 ADP_CNTL17 Advanced Data Path ADP Control register 14 15 16 and 17 These regi...

Страница 50: ...he threshold rapidly and randomly so the screen will quickly flip back and forth between the 0 and the 90 orientations This problem is avoided in the KX132 1211 by choosing a 30 threshold angle With a...

Страница 51: ...her the face up or face down orientation depending on the sign of the z axis The KX132 1211 will only change the screen orientation when the orientation angle is above the factory defaulted user defin...

Страница 52: ...threshold for wake up or back to sleep functionality respectively Note that each Wake Up Function Counter WUFC count qualifies 1 one user defined Wake Up Function ODR period as set by OWUF 2 0 bits in...

Страница 53: ...state On the other hand if the high pass filtered acceleration on any axis is less than the user defined Back to Sleep Threshold BTSTH the device has transitioned from an active state to an inactive...

Страница 54: ...rupt was issued on the next clock cycle 17th clock cycle In the example since the interrupt was set to active low the interrupt line was pulled low to indicate an interrupt The operation of the back t...

Страница 55: ...before with the only difference being that each acceleration sample is being compared to the same user defined wake up threshold WUFTH or back to sleep threshold BTSTH regardless of previous sample On...

Страница 56: ...ionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 56 of 73 Examples 2 2 1 3 Case 1 XPWUE 1 XNWUE 0 C_MODE 0 PR_MODE 0 Positive d...

Страница 57: ...19 Kionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 57 of 73 2 2 1 4 Case 2 XPWUE 0 XNWUE 1 C_MODE 0 PR_MODE 0 Positive direct...

Страница 58: ...Kionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 58 of 73 2 2 1 5 Case 3 XPWUE 1 XNWUE 0 C_MODE 1 PR_MODE 0 Positive direction...

Страница 59: ...19 Kionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 59 of 73 2 2 1 6 Case 4 XPWUE 1 XNWUE 1 C_MODE 0 PR_MODE 0 Positive direct...

Страница 60: ...19 Kionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 60 of 73 2 2 1 7 Case 5 XPWUE 1 XNWUE 1 C_MODE 0 PR_MODE 1 Positive direct...

Страница 61: ...lectable ODR are used to configure the KX132 1211 for a desired tap detection response Performance Index The Directional TapTM detection algorithm uses low and high thresholds to help determine when a...

Страница 62: ...e time period that a tap event will only be characterized as a single tap A second tap must occur outside of the latency timer If a second tap occurs inside the latency time it will be ignored as it o...

Страница 63: ...index TTL inside the TWS period and ends outside the TDTC This means that the TDTC determines the minimum time separation that must exist between the two taps of a double tap event Similar to the sing...

Страница 64: ...value independent of the actual g range setting of the device Equation 8 shows how to calculate the FFTH register value for a desired Free fall threshold The threshold of 0 5g is a good starting poin...

Страница 65: ...l Interrupt Example FFCNTL ULMODE 1 Figure 21 Typical Free fall Interrupt Example FFCNTL ULMODE 0 Neg Motion limit 0g 216 128 40 Typical Freefall Interrupt Example nonLatching 108 148 255 Pos Motion l...

Страница 66: ...f samples This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples calculated with Equation 10 BUF_RES 0 SMPX SMP_LEV 9 0 3 SMP_TH 7 0 BUF_RES 1 SMPX SMP_LE...

Страница 67: ...22 represents a high resolution 3 axis sample within the buffer Figure 23 Figure 30 represent a 10 sample version of the buffer for simplicity with Sample Threshold set to 8 Regardless of the selecte...

Страница 68: ...0 FIFO read pointer 1 Data1 2 Data2 3 Data3 4 Data4 5 Data5 6 Data6 buffer write pointer 7 Sample Threshold 8 9 Figure 24 Buffer Approaching Sample Threshold In FIFO and Stream modes a watermark inter...

Страница 69: ...n out to make room for Data8 Index Sample 0 Data1 Trigger read pointer 1 Data2 2 Data3 3 Data4 4 Data5 5 Data6 6 Data7 Trigger write pointer 7 Data8 Sample Threshold 8 9 Figure 26 Additional Data Prio...

Страница 70: ...d operation mode FIFO and Trigger modes stop accumulating samples when the buffer is full and Stream mode begins discarding the oldest data when new samples are accumulated Index Sample 0 Data0 FIFO r...

Страница 71: ...12874 1907311402 0 17 www kionix com info kionix com Page 71 of 73 In FIFO Stream or Trigger mode reading one sample from the buffer will remove the oldest sample and effectively shift the entire buf...

Страница 72: ...2019 Kionix All Rights Reserved tel 607 257 1080 fax 607 257 1146 893 12874 1907311402 0 17 www kionix com info kionix com Page 72 of 73 2 6 Advanced Data Path Feature Please refer to AN109 Introducti...

Страница 73: ...ix is a registered trademark of Kionix Inc Products described herein are protected by patents issued or pending No license is granted by implication or otherwise under any patent or other rights of Ki...

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