Rohm BU7963GUW, Технические заметки

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Technical Note
6/19
BU7963GUW
www.rohm.com
2010.04 - Rev.A
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A B C
DVDD
DVDD
MSVDD
D
DVDD
Table 4. Parallel Data Interface
Parallel Data Interface 29-pin
Name Width Level I/O Functions Shutdown
Equivalent
Schematic
PCLK 1 CMOS I PCLK interface. Input A
PD[26:0] 27 CMOS I Parallel data interface. Input A
CKD 1 CMOS O
Output of PCLK detection result.
‘L’: clock stop.
‘H’: clock detect.
‘L’ C
Table 5. Control
Control 8-pin
Name Width Level I/O Functions Shutdown
Equivalent
Schematic
XSD 1 CMOS I
Shutdown pin.
‘L’: shutdown.
‘H’: normal operation.
Input A
LS0 1
CMOS I
Selection of the number of data channel and
the data format.
＊
Refer to "Selection of the number of
MSDL3 channels".
＊
Set the same number of data channel
between the TX device and the RX device.
Input A
LS1 1
RVS 1 CMOS I
Selection of MSDL3 pins assignment.
‘L’: Default matrix.
‘H’: Flipped matrix.
Input A
PLL_BW 1 CMOS I Selection of PLL bandwidth. Input A
POL_PCLK 1 CMOS I
Selection of input clock polarity.
‘L’: sample parallel data at falling.
‘H’: sample parallel data at rising.
Input A
TEST0 1
Pull
down
I
Test mode pin.
‘L’: normal mode.
‘H’: test mode.
Must be ‘L.’
Input
B
TEST1 1 B
Fig.4. Equivalent Schematics