Rohm BU7858KN, Техническая заметка

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Writing Protocol
The write protocol is shown below. The register address is transferred in a byte after the slave address and write
command are transferred. The third byte writes the data into the internal register that is indicated by the second byte. After
that, the register address is incremented on automatically (when the register address is between 00h and 16h). However,
when the register address reaches 16h, the register address does not change with the next byte transfer, rather, it accesses
the same register address (16h). The register address is incremented after transfer completion.
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Reading Protocol
It reads from the next byte after writing the slave address and R/W bit. The read register is the following address
accessed at the end. After that, the data of the address incremented is read out. The register addresses are incremented
after transfer completion.
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Combined Reading Protocol
After specifying an internal address, it reads by generating resending start conditions and changing the direction of data
transfer. Afterwards, data from incremented addresses is read. The register addresses are incremented after transfer
completion. Compound writing is possible by writing R/W=0 after resending start condition.
S A A A
P
from master to slave
from slave to master
A=Acknowledge
A=Non-acknowledge
S=START condition
P=STOP condition
Sr=Repeated START condition
R/W=0 ( Write)
Sr 1
R/W=1 ( Read)
A
Slave address
1 0 1 0 0 1 0 1
Register address
A7 A6 A5 A4 A3 A2 A1 A0
Slave address
1 0 1 0 0 1 1
Data Data
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 A
Register address
Increment
Register address
Increment
S A A A P
Data Register address Slave address
from master to slave
R/W=0(Write)
Data
A D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 1 0 1 0 0 1 0 1
Register address
Increment
Register address
Increment
A=Acknowledge
A=Non-Acknowledge
S=START condition
P=STOP condition
from slave to master
1 S A P
R/W=1(Read)
Data
A A
Slave address
1 0 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Register address
Increment
Data
Register address
Increment
from master to slave
A=Acknowledge
A=Non-Acnkowledge
S=START condition
P=STOP condition
from slave to master