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Programming and Parameters
PowerFlex 700S Phase II AC Drive User Manual -
Publication 20D-UM006G-EN-P – July 2008
261 Steg&Hiedn
TPSel
[Steg&Hiedn TPDta].
•
Hh0 Edge Time - Latency counter value, not used for Hi-Resolution Feedback Option.
•
Hh0 dEdge - Change in edge counts for one 500 microsecond update. At constant speed,
this value should be constant.
•
Hh0 dTime - Change in update time. This value should be constant, 500 microseconds.
•
Hh0 EPR - This value should be 1,048,576 counts per revolution-this is a constant value.
•
Hh0 nMax - This is a scaled value of 2.
•
Hho Delta2Err - Derivative of value 2.
Default:
Options:
0 =
0 =
1 =
2 =
3 =
4 =
5 =
6 =
7 =
8 =
9 =
“Zero”
“Zero”
10 = “Reserved”
“St0 EdgeTime”
11 = “Hh0 EdgeTime”
“St0 dEdge”
12 = “Hh0 dEdge”
“St0 dTime”
13 = “Hh0 dTime”
“St0 EPR”
14 = “Hh0 EPR”
“St0 EdgeMode”
15 = “Hh0 EdgeMode”
“St0 nMax”
16 = “Hh0 nMax”
“St0 Delta2Er”
17 = “Hh0 Delta2Er”
“Reserved”
“Reserved”
262 Steg&Hiedn
TPDta
[Stegmann0 Status].
Default:
Min/Max:
0
-/+32768
RO 16-bit
Integer
263
Heidenhain0 Cnfg
Configures the Heidenhain Encoder Feedback Option.
•
Bit 5 “Direction” determines the counting direction. Set to “0” to count up or forward. Set to “1” to count in reverse or down.
•
Bit 6 “SW Reset” setting this bit to “1” resets and restarts the option card.
•
Bit 7 “VM Direction” determines the direction of the encoder pulse output from the Heidenhain option card when bit 6 “VrtlMasterEn” of
[Heidn Encdr
Type] is set. When this bit is off, = “0”, the direction of the encoder pulse output is the same as
[Heidn VM Pos Ref], and the reverse of Par 1155 when
this bit is set, = “1”.
•
Bits 10 -12 form a 3 bit moving average filter sampling rate. (See
Table 263A: Sample Rate Bit Settings
Notes: This parameter was added for firmware version 2.03. This parameter was changed to non-linkable for firmware version 3.01. Added bit 7 for firmware
version 4.001.
No.
Name
Description
Values
Linkab
le
R
ead-Wr
ite
Da
ta
T
ype
Options
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
SmplRate bt2
SmplRate bt1
SmplRate bt0
Res
er
ved
Res
er
ved
VM Direc
tion
SW R
eset
Dire
ction
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0 = False
1 = True
Table 263A: Sample Rate Bit Settings
Bit 12 11 10 Exponent Value ‘n’ Filter Sample Size = 2
n
0
0
0
0
1
0
0
1
1
2
0
1
0
2
4
0
1
1
3
8 (Default)
1
0
0
4
16
1
0
1
5
32
1
1
0
6
64
1
1
1
7
127
Содержание PowerFlex 700S
Страница 1: ...USER MANUAL Firmware Versions 1 xxx 4 002 PowerFlex 700S High Performance AC Drive Phase II Control ...
Страница 58: ...2 8 Start Up PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 Notes ...
Страница 147: ...Programming and Parameters 3 89 PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 ...
Страница 278: ...D 8 HIM Overview PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 Notes ...
Страница 316: ...Index 6 PowerFlex 700S Phase II AC Drive User Manual Publication 20D UM006G EN P July 2008 ...
Страница 317: ......