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3-78 Programming and Parameters
PowerFlex 700S Phase II AC Drive User Manual - Publication 20D-UM006G-EN-P – July 2008
555 MC Status
Indicates the status of the Motor Control (MC) Processor and related functions.
Note: Changed bit 18 from “Reserved” to “Vqs Reg Act” for firmware version 3.03.
556 Trend Control
Set bits to configure the Data Trend function:
•
Bit 0 “Enbl Collect” - Trend data collection begins on the rising edge of this bit and continues until either this bit is set low or the trend data has been completely
collected. This bit should be cleared following either the 'Triggered' status or 'Complete' status in order to complete the trend sequence. This bit can also be
cleared at any time to force the trend data sampling to stop and set the 'Complete' status bit.
•
Setting bit 1 “In1 Real” - specifies the Real data type for Trend Input 1. The source for Real data is Par 571 [Trend In1 Real]. Clearing the bit specifies the Integer
data type. The source for Integer data is Par 570 [Trend In1 DInt].
•
Setting bit 2 “In2 Real” - specifies the Real data type for Trend Input 2. The source for Real data is Par 575 [Trend In2 Real]. Clearing the bit specifies the Integer
data type. The source for Integer data is Par 574 [Trend In2 DInt].
•
Setting bit 3 “In3 Real” - specifies the Real data type for Trend Input 3. The source for Real data is Par 579 [Trend In3 Real]. Clearing the bit specifies the Integer
data type. The source for Integer data is Par 578 [Trend In3 DInt].
•
Setting bit 4 “In4 Real” - specifies the Real data type for Trend Input 4. The source for Real data is Par 583 [Trend In4 Real]. Clearing the bit specifies the Integer
data type. The source for Integer data is Par 582 [Trend In4 DInt].
•
Setting bit 15 “Auto Output” causes the trend output parameters to automatically cycle through the entire trend buffer at the rate specified in Par 559 [Trend
Rate]. Typically, you link the output to an analog output for display on an oscilloscope.
•
Auto output is accomplished by writing to Par 569 [TrendBuffPointer]. Clearing this bit requires manual selection of Par 569 [TrendBuffPointer] to view the trend
buffer contents.
557 Trend Status
Bits indicate the status of the Data Trend function:
•
Bit 1 “Triggered” indicates a Trend Trigger event has been detected. This bit will clear in response to the rise of Par 556 [Trend Control], bit 0 “Enbl Collect”.
•
Bit 2 “Complete” indicates all the post trigger data samples have been gathered and the trend buffers are full. It will also be set if the Par 556 [Trend Control], bit
0 “Enbl Collect” is cleared before the trigger occurs. The trend data outputs will be updated from the contents of the trend buffer data when this bit is set. Par 556
[Trend Control], bit 0 “Enbl Collect” can be cleared after this bit is set without affecting the trend data buffer contents. This bit will clear in response to the rise of
Par 556 [Trend Control], bit 0 “Enbl Collect”. The trend outputs will be forced to zero while this bit is clear.
No.
Name
Description
Values
Linkab
le
R
ead-Wr
ite
Da
ta
T
ype
Options
Min
Vq
s
MaxDCB
us Vqs
MaxMot
or
V
qs
Max Vds Min
Vd
s
SrL
ssWs
Limi
t
Slip Limit Regen Iqs
L
imi
t
FldW
eak
ening
MC F
W
Gr
oup2
Rese
rv
ed
Rese
rv
ed
Vqs Reg
Ac
t
FluxRa
tioRef
Command
Lim
DC B
us
Lo
w
MC T
est Mo
de
Pre
C
hr
g Re
q
PWM En Pre
C
hr
g Do
ne
Flux En To
rque En
Chang
e Dir
MC Co
mmis
F
lt
MC Co
mmis
R
un
MC F
ault
MC Re
ady
Base
Blo
ckRe
q
To
rqueRu
nReq
Flux Run Req MC En
Re
q
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = False
1 = True
Options
A
uto Out
put
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
Res
er
ve
d
In
4
R
eal
In
3
R
eal
In
2
R
eal
In
1
R
eal
Enb
l Collect
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = False
1 = True
Options
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Res
er
ved
Complete Tr
igge
red
Res
er
ved
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 = False
1 = True