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RK3288 Hardware Design Guide

7 CPU&PMU

7.1 Schematic

RK3288 only need an external 24MHz crystal as shown in Fig 7-1. This crystal Y1100

requires frequency offset =<±20ppm, temperature offset =<±30ppm. The value of load
capacitors C1101, C1102 should be selected according to actual load capacitance of crystal.

8pF is the corresponding value of crystal selected by us, it is not the common value.

To decrease the circuit area of crystal, reduce its internal PLL clock jitter and avoid large

clock jitter caused by unreasonable signal return path design, RK3288 clock signal is
referenced to ground OSC_XVSS pin. This design has a certain demand for PCB layout, if user

don't need to reserve adjustment space, R1102 can be removed and connect OSC_SVSS to
GND network.

When RK3288 accesses to deep sleep mode, internal clock source will be switched to

external 32.768 KHz signal, system power consumption will be reduced by lower operating

frequency, and this signal will be obtained from PMIC or external RTC clock source.

Fig 7-1

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Содержание RK32 Series

Страница 1: ...RK3288 Hardware Design Guide RK3288 Hardware Design Guide Revision 1 2 Jun 18 2014...

Страница 2: ...RK3288 Hardware Design Guide Revision History Date Revision Description 2014 12 15 1 2...

Страница 3: ...ic 42 7 2 PCB Layout 43 8 DDR Controler DRAM 44 8 1 Schematic 44 8 2 PCB Layout DDR0 channel DDR1 channel 49 9 Flash control Memory 52 9 1 Schematic 52 9 2 PCB Layout 55 10 TF Card 57 10 1 Schematic 5...

Страница 4: ...90 20 1 Schematic 90 21 MAC 91 21 1 Schematic 91 21 2 PCB Layout 94 22 2G 3G 4G 99 22 1 Schematic 99 22 2 PCB Layout 100 23 WIFI BT 103 23 1 Schematic 103 23 2 PCB Layout 105 24 GPS 112 24 1 PCB Layo...

Страница 5: ...rt Copyright and Patent Right Information in this document is provided solely to enable system and software implementers to use Rockchip Electronics Co Ltd s products There are no expressed or implied...

Страница 6: ...peripheral interface to support flexible outputs such as dual channel LVDS dual channel MIPI DSI eDP1 1 HDMI2 0 also supports dual channel MIPI CSI2 interface capable of ISP with 1 3 million pixels R...

Страница 7: ...for GPU computing Support OpenGL ES1 1 2 0 3 0 OpenVG1 1 OpenCL1 1 and Renderscript Directx11 DVFS support 2D GPU Multi Core architecture Up to 8Kx8K input and 4Kx4K output High quality image scale up...

Страница 8: ...nnel MIPI DSI HDMI2 0 to support maximum 4Kx2K display Optional eDP1 1 interface Memory Interface Nand Flash Interface Dual channel 8bits per channel Compatible with all of SLC MLC TLC Nand Flash incl...

Страница 9: ...e GPS baseband interface PS 2 master interface 5 UART 3 SPI master or slave 6 I2C up to 4Mbps 5 PWM Others Standalone crypto and decrypto compatible with AES 128bits DES 3DES SHA 1 SHA 256 MD5 160bits...

Страница 10: ...h module should be packaged within its own domain In order to avoid too many schematic versions as well as repeated corrections function modules is designed in separated pages and groups and add some...

Страница 11: ...c LCM 10 05 eDP 2560 x 1600 Front Camera OV2659 Rear Camera MIPI FX288A R2 0 OV8825 HDMI Yes Type C USB OTG 2 0 Micro B TF Card Yes Audio Codec Yes Microphone Yes Audio Jack Yes Vibration Yes G Sensor...

Страница 12: ...o use 1 cell battery for lower cost Another example customer raises below request RK3288 Sample Plan Two DC 5V Fire Bull Charger No USB Charger Yes Battery 1 Cell DRAM 2 x 32bit LPDDR2 POP Package FLA...

Страница 13: ...crophone Yes Audio Jack Yes Vibration Yes G Sensor Yes Gyroscope Yes WIFI Module 802 11 a b g n BT 4 0 GPS Yes 3G Yes 4G No Efuse Yes Based on this requirement complete schematic can be finalized by o...

Страница 14: ...Permittivity Remark Top Signal1 Cu 0 7 Plating to 1oz pp FR 4 3 8 4 3 L2 Gnd1 Cu 1 5 1oz core FR 4 8 4 3 L3 Signal2 Cu 1 5 1oz PP FR 4 4 3 Adjust according to thickness L4 Power Cu 1 5 1oz core FR 4 8...

Страница 15: ...lanning state recommend to choose the design in which capacitors can be placed on the reverse side of CPU The size of vias under CPU is 0 2mm 0 35mm inside outside diameter In order to suppress EMI th...

Страница 16: ...at dissipation effect If space is allowed reserve a shielding case space on BOTTOM layer as well or reserve a big GND area with solder mask for shielding of coordination structure Copper integrity Int...

Страница 17: ...to reduce trace to trace crosstalk If the clearance is not less than 3 times of trace width it can reduce crosstalk between the traces up to 70 20H Principle Shrink power supply layer which can makes...

Страница 18: ...points on EMMC_CLKO FLASH_CLE signal for eMMC Nand Flash it will be more convenient to enter maskrom burning mode for debugging Fig 3 5 Suggest to add signal test points to interfaces like camera TP...

Страница 19: ...ins etc Add obvious remark for CPU 1st pin without overlapped or hidden under device Make sure component package size is properly within height limit Make sure welding direction especially for sink st...

Страница 20: ...uld be placed respectively keep trace as short wide as possible for large current sources Due to radiation diffusion characteristics of thermal heat source should be the center of CPU heat sink make h...

Страница 21: ...een this will cause image color piece due to partial overheat from long time operation For devices with metal rear cover better to transfer CPU heat to rear cover through thermal silica For devices wi...

Страница 22: ...RK3288 Hardware Design Guide Fig 4 3 Fig 4 4...

Страница 23: ...RK3288 Hardware Design Guide Fig 4 5...

Страница 24: ...45uF capacitor value of VDD_GPU is 66uF and the large value capacitors should be placed on the reverse side or near CPU to ensure power ripple within 100mV in case that power ripple is too large in co...

Страница 25: ...RK3288 Hardware Design Guide Coupling capacitor of chip in schematic should be placed close to the pin of chip as shown in Fig 5 3 5 4 Fig 5 3 Fig 5 4...

Страница 26: ...ent capacity and reduce the trace impedance as shown in Fig 5 5 Fig 5 5 Place enough vias in the power trace layer change node to enhance the current capacity and reduce the trace impedance as shown i...

Страница 27: ...layer or other layers Fig 5 7 The large capacitors should be located in far end load end of VDD_CPU VDD_GPU VDD_LOG VCC_DDR power Place more than 40uF capacitors on the reverse side or close to CPU o...

Страница 28: ...power copper Below is Formula based on experience 75 0 44 0 A KT I K is a correction factor outer copper surface is 0 048 while inner is 0 024 T is the allowable maximum temperature rise with unit Ce...

Страница 29: ...hole is about 420mA For 5 A current at least 13 vias with 0 2mm aperture requested If area is limited enlarging aperture can decrease the number of holes 5 3 SYR827 SYR828 PCB Layout Guide SYR827 SYR8...

Страница 30: ...C current resistance is less than 20mR In order to improve output power suggest to use inductor the value of which ranges from 0 22uH to 0 24uH In actual test if 0 22uH inductor is used power ripple i...

Страница 31: ...ance of route management is 60mR the total volume will easily exceed 150mR 150mR 3 5A 0 525V which means the huge voltage will be lost in transmission route which will reduce application efficiency of...

Страница 32: ...ors one of them is sample resistor of charging current as shown in Fig 5 16 both ends of R2166 should be differentially routed to pads of C4 and C5 as shown in blue trace in Fig 5 17 notice don t conn...

Страница 33: ...shown in Fig 5 18 R2120 must be placed close to R2119 in Layout R2120 can t be connected to GND and it should be separated from GND copper by keepout and be routed to pad of R2119 separately ICP and...

Страница 34: ...e ADP port first so trace from USB port to ADP port should be wider 5 5 PMIC ACT8846 To optimize 1 cell battery solution it is suggested to use 2 cell battery solution with ACT8846 BQ24133 as charger...

Страница 35: ...e is two sample resistors in RK818 one is the current sample resistor R2340 close to battery and the other one is sample resistor R2342 on differential lines as shown in Fig 5 23 The second pin of R23...

Страница 36: ...RK3288 Hardware Design Guide Fig 5 24 To improve the sampling accuracy of battery capacitor C2363 in feedback circuit should be placed close to the pin of RK818 as shown in Fig 5 25 Fig 5 25...

Страница 37: ...o ePAD under the chip and enough via holes should be placed around ePAD as shown in Fig 5 26 Fig 5 26 The clearance between inductors SW5 and SW6 should be more than 1 6 mm or high voltage caused by m...

Страница 38: ...talk from other signals will cause voltage instability and oscillation as shown in Fig 5 29 Fig 5 29 All input and output capacitors should be placed close to RK818 and enough via holes should be plac...

Страница 39: ...RK3288 Hardware Design Guide Fig 5 30...

Страница 40: ...up or down as an input and it can be configurable and closed after power on as shown in figure 6 1 _d remarked in schematic diagram is an default for internal pull down _u is pull up Any modification...

Страница 41: ...ifferent power supply 1 8V 2 5V or 3 3V can be adjusted its intensity of output driving through modifying regulator name in dts file as shown in Fig 6 4 Please consult with RK engineers about any furt...

Страница 42: ...cuit area of crystal reduce its internal PLL clock jitter and avoid large clock jitter caused by unreasonable signal return path design RK3288 clock signal is referenced to ground OSC_XVSS pin This de...

Страница 43: ...tal If OSC_XVSS is used as clock ground crystal should be placed close to CPU and it is reference plane for crystal route as shown in Fig 7 2 Fig 7 2 If GND is used as clock ground crystal should be p...

Страница 44: ...The rest signals can be divided into three groups GROUP E Address ADDR0 ADDR14 GROUP G Control including WE CAS RAS CS0 CS1 CKE0 CKE1 ODT0 ODT1 BA0 BA1 BA2 etc GROUP F Clock differential pair of CLK a...

Страница 45: ...8 Hardware Design Guide Fig 8 1 For DDR3 four groups data GROUP A B C D can be exchanged in group Moreover each data in GROUP A B C D eg DDR0_D0 D7 also can be exchanged with each other as shown in Fi...

Страница 46: ...ust match A or B channel DDR0_D0 D7 in LPDDR2 3 meanwhile DDR0_D0 D7 is one to one correspondence Other GROUP GROUP B C D can be exchanged in group Moreover each data in GROUP B C D eg DDR0_D8 D18 als...

Страница 47: ...stors R1204 120K and R1206 120K for DDR3 mode as shown in Fig 8 4 Please adjust the value of R1204 100K and R1206 82K for LPDDR2 3 mode Fig 8 4 The divider resistor value of reference power supply sho...

Страница 48: ...e placed close to the branch point of DDR clock trace as possible Fig 8 6 VCC_DDRC is turned off by MOS Transistor in order to reduce power consumption in deep sleep as shown in Fig 8 7 In LPDDR2 3 mo...

Страница 49: ...ls length tolerance of DATAn and DQSnP DQSnM in each GROUP A B C D is better The length tolerance between GROUP data and GROUP data should be limited within 120mils The length tolerance between GROUP...

Страница 50: ...extremely small current input current is almost 3mA 1nF bypass capacitors should be added close to each pin of VREF capacitor quantity for each trace should be less than 5 to reduce influence of powe...

Страница 51: ...learance between two vias should be equal to or more than 32mils The size of vias is 0 2mm for drill and 0 4mm for diameter Set copper layer as split mixed Set the safe clearance between via and coppe...

Страница 52: ...pply VCC_FLASH may be 1 8V eMMC4 1 above version or 3 3V please adjust it based on Datasheet and verify FLASH0_VOLTAGE_SEL pull up and pull down status as shown in Table 9 1 Tips When eMMC is in use s...

Страница 53: ...hiba and SanDisk DDR VCCQ1 and VCCQ4 need to be connected to VCC_IO for power supply which means R4001 R4003 R4004 R4005 should be SMT with OR resistor Fig 9 2 If eMMC Flash is in use as shown in belo...

Страница 54: ...ble with components below eMMC 4 1 which means product materials have more choices Fig 9 4 For better to enter MaskRom hardware burning mode need update LOADER in Developing stage FLASH_CLE should res...

Страница 55: ...inch In order to improve stability and compatibility of SDIO suggest to use the adaptive algorithms of driven strength and Timing Tuning Flash power ripple should be controlled within 80mV and it pow...

Страница 56: ...RK3288 Hardware Design Guide Fig 9 7 Fig 9 8...

Страница 57: ...ge of VCCIO_SD and VCC_SD is 3 3V When SD2 0 card is inserted VCC_SD and VCCIO_SD is always 3 3V while for SD3 0 card VCC_SD will turn to 1 8V to meet high speed card LDO in the card supplies 1 8V for...

Страница 58: ...D data traces are required to be surrounded by GND the same for CLK which should be routed respectively On the RK3288 platform traces length of TF card should be limited within 12 4 inch In order to i...

Страница 59: ...HOST external interface HOST1 supports USB 2 0 specification only while HOST2 supports both USB 2 0 and 1 1 specifications HOST2 interface is considered to be used in BOX solution as first priority F...

Страница 60: ...ed as close as possible to CPU to shorten trace length USB signal trace should be fully compliant with differential specification trace corner should be an arc or obtuse angle not be a right or acute...

Страница 61: ...rs as possible which will cause discontinuousness of impedance The current defined in USB 2 0 specifications is 500mA but 1A is required for VBUS trace to protect from over current If USB interface is...

Страница 62: ...RK3288 Hardware Design Guide Fig 11 7...

Страница 63: ...f USB device is detected by PC upon release of button ADC_IN1 will recover high level 1 8V then firmware updating is available On RK3288 SARADC sampling range is 0 1 8V sampling accuracy is 10bit Inpu...

Страница 64: ...uld be placed close to Key to fulfill electrostatic protection as shown in Fig 12 2 Key buffeting eliminated capacitor C1501 should be placed close to Chip Trace of ADKEY_IN should be separated with o...

Страница 65: ...d keep it in the same level with I2C pull up level otherwise it will cause Camera abnormal or disabled working status as shown in Fig 13 1 Fig 13 1 In order to avoid camera trace length is too long wh...

Страница 66: ...the same time since RK3288 has only one CUP with ISP only one of two DVP SOC Sensor can be RAW Sensor another one must be MIPI Sensor RK3288 supports dual MIPI Sensor input recommendations for MIPI C...

Страница 67: ...mil Take trace corner always as an arc or obtuse angle not a right angle or acute angle impedance is Z 100ohm 10ohm To reduce EMI high speed differential signal of MIPI Sensor should be placed on inne...

Страница 68: ...14 Display Interface 14 1 Schematic RK3288 support many video output mode such as Parallel RGB LVDS MIPI eDP HDMI etc 1 accuracy reference resistor should be taken for MIPI LVDS HDMI PHY as shown in F...

Страница 69: ...RK3288 Hardware Design Guide Fig 14 2 Fig 14 3...

Страница 70: ...MIPI_TX_AVDD_1V8 and MIPI_TX RX_AVDD_1V8 are the same group of power they share same power supply When LVDS and RGB are using LVDS_AVDD_1V0 LVDS_AVDD_1V8 and LVDS_AVDD_3V3 need power supply otherwise...

Страница 71: ...he RK3288 each display module has its own power supply and power pins of each module should be packaged within its own domain No power supplied to the module which is not in using to reduce power cons...

Страница 72: ...e Fig 14 8 Make sure LCDC_VDD has regular power supply or HDMI will not display as pin V20 shown in Fig 14 9 Fig 14 9 As shown in Fig 14 10 decoupling capacitor of each module power should be placed c...

Страница 73: ...ed within 10 inch include the length of PCB layout FPC connecting lines and receiver traces no more than 15 inch or it will affect signal quality On the RK3288 platform traces length of eDP network sh...

Страница 74: ...RK3288 Hardware Design Guide Fig 14 11 Coupling capacitor of eDP data output channel should be placed close to chip as shown in Fig 14 12 Fig 14 12...

Страница 75: ...MT 7 85 smaller screen can chose 1 cell battery solution with R5003 SMT Fig 15 1 Place pull up and pull down resistors R5000 R5001 and coupling capacitor C5000 C5001 which is on AUXN AUXP auxiliary ch...

Страница 76: ..._TX as left output channel and MIPI_TX RX as right output channel which cannot be switched as shown in Fig 15 3 15 4 If MIPI screen channels can be switched this problem doesn t exist for more details...

Страница 77: ...ntrolled by CPU PWM and if PWM duty ratio is higher screen brightness is lower if CABC is in use 0R resistor R5107 R5108 should be SMT inverter U5101 and resistance R5109 R5110 can be decided to SMT o...

Страница 78: ...PCB Layout High speed signal trace design is referenced to section 12 of PCB Layout Backlight current limiting resistors R5006 R5007 and power capacitor C5004 should be placed close to screen base as...

Страница 79: ...RK3288 Hardware Design Guide...

Страница 80: ...In actual product application this interface is not suggested to be used for other functions design is shown as in Fig 16 1 Fig 16 1 If level conversion chip RS232 is used TXD RXD direction is an impo...

Страница 81: ...y region feeds APIO4_VDD in practical produce design actual IO power supply requirement based on Codec choose a corresponding supply circuit 1 8V or 3 3V and remains equal to pull up level of I2C othe...

Страница 82: ...n as shown in Fig 17 3 Fig 17 3 If Codec chooses decoupling capacitor for output in ideal condition 100uF capacitor can ensure flatness of frequency response test curve If smaller decoupling capacitor...

Страница 83: ...signals HP output signal line width suggested to be above 15mils LINE in out signal trace width suggested to be above 10mils MIC input signal is sensitive MIC coupling capacitor should be placed close...

Страница 84: ...anel I2C to TP power supply VCC_TP to avoid increasing extra power consumption by power electric leakage from I2C bus to TP screen Fig 18 1 Pay attention to the withstand voltage of Charge Pump capaci...

Страница 85: ...gn Guide 18 2 PCB Layout It is easy to destroy data cables of CPU by ESD of big screen so sensor signal lines need to be protected In the design of TP onboard sensor and driver signals should be separ...

Страница 86: ...bus is in accordance with VCCIO supply of sensor otherwise voltage matching is required Fig 19 1 Hall Sensor contains unipolar and all pole Please choose the device of suitable type according to the...

Страница 87: ...2 Motor is inductive device It s necessary to add diode and pay attention to its direction Fig 19 3 The gravity sensor includes three compatibility design SMT can be according to actual needs to meet...

Страница 88: ...era and don t place any other luminous bodies near it as shown in Fig 19 5 Fig 19 5 Illumination value received by light sensor is determined by the size of TP silk screen hole and ink light transmitt...

Страница 89: ...netic field easy magnetization devices large current devices etc such as handset loudspeaker motor camera large value inductor etc Please pay attention to the placement direction of the gravity sensor...

Страница 90: ...the eFUSE embedded in RK3288 need add eFUSE power supply circuit as shown in Fig 20 1 This parts of circuit can be omitted if it is not essential Suggest customers to reserve two test points on PCBA...

Страница 91: ...Schematic Ethernet and FLASH1 are reusable if Ethernet is used then FLASH1 can t be used at the same time MAC supports RMII and RGMII these two interfaces Fig 21 1 is for Gigabit RGMII interface Fig...

Страница 92: ...itors C251 C252 should be base on nominal loading capacity of the adopted crystal 12pF matches the crystal we have chosen it is not the common value Fig 21 3 L9 inductor in Fig 21 4 should meet the fo...

Страница 93: ...mode choke Common mode choke is 90 120ohm as shown in Fig21 5 Fig 21 5 Suggest to use RJ45 base with metal shield If RJ45 has LED light LED0 2 need to be reserved a 100pF capacitor to earth reduce EM...

Страница 94: ...he whole layout must follow below principles The closer PHY has been put to RK3288 the EMI will be less which means RGMII trace is the shorter EMI will be less and it must be controlled within 15cm Be...

Страница 95: ...impedance is Z 100ohm 10ohm trace should be as short as possible the total length of differential trace should be shorter than 12CM make a complete reference plane if reference plane is not complete...

Страница 96: ...close to PHY and should be surrounded by GND with as short trace as possible and have a complete reference plane Fig 21 11 RSET resistor R151 must be placed close to PHY less than 800mil and keep it f...

Страница 97: ...0mil make the trace as short as possible the whole trace length must be limited within 15CM Ensure a complete reference plane Fig 21 13 As shown in below Fig concatenating resistor should be located c...

Страница 98: ...note of internal Switching Regulator LAYOUT Capacitors C270 C271 of Power supply VDDREG should be placed close to PIN44 and PIN45 line width should be less than 40mil Place L9 C260 close to PIN48 lin...

Страница 99: ...e power domain for GPIO in actual product design IO power is supplied based on 4G module make sure GPIO level can match 4G module as shown in Fig 22 1 22 2 Fig 22 1 Fig 22 2 Reserve ESD component for...

Страница 100: ...nded by GND The transient current can reach more than 1 8A when the 3G module is transmitting with its max power It s suggested that DCDC with large current or MOS with low internal resistance should...

Страница 101: ...of the width of 3G antenna and microstrip the impedance requirement is Z 50 10ohm Under the traces a complete reference plane is needed to serve as a reference GND to RF signal The longer 3G trace is...

Страница 102: ...RK3288 Hardware Design Guide Fig 22 7...

Страница 103: ...controller must keep the same with VIO module as shown in Fig 23 1 23 2 Tips On the circumstance of SDIO 3 0 APIO3_VDD power supply must be 1 8V Fig 23 1 Fig 23 2 WIFI RTC_CLOCK should be matched wit...

Страница 104: ...oose the appropriate value of the matching capacitor of crystal oscillator according to the crystal oscillator specification to avoid frequency deviation is too large to work normally such as the numb...

Страница 105: ...be surrounded by GND If there is enough space CLK is suggested to be surrounded by GND separately Meanwhile avoid routing close to power supply or high speed signal trace Any of two signal route in on...

Страница 106: ...the VBAT and VDDIO power pins of module and to be placed on the same plane with the module as much as possible Fig 23 8 As shown in Fig 23 9 23 10 the source inductor L6100 and the source capacitor C...

Страница 107: ...e module should reserve a complete GND without other signal traces as shown in Fig 23 11 Fig 23 11 Reserve a complete GND under the crystal oscillator without other signal traces and place enough via...

Страница 108: ...ve as a reference GND to RF signal The longer 3G trace is the greater energy lose Therefore the length of antenna is as shorter as possible in the design of RF antenna meanwhile branches and vias are...

Страница 109: ...RK3288 Hardware Design Guide Fig 23 13 Fig 23 14...

Страница 110: ...3 16 Don t put them in the place where hands hold and keep them away from the metal devices as far as possible Impedance matching is required for antenna Don t twist the antenna together with the batt...

Страница 111: ...n t be too long in case of excessive RF energy loss The feeder length is suggested to be less than 7 cm and don t strip too much shielding mesh when stripping feeders which will cause the discontinuou...

Страница 112: ...perating frequencies of 2G and 3G modules are not in the working band of GPS their working peak power is large and sometimes they work together with GPS at the same time So it is easy to cause the inp...

Страница 113: ...nce control is relatively high because of the high receiving sensitivity of GPS 140dbm The bad impedance control will cause poor VSWR and Return Loss which will directly affect the performance of GPS...

Страница 114: ...ce length of antenna can t be shorter than 12mil Fig 25 1 Put the NFC antenna on battery and use special absorbing material between them in order to avoid affecting the sensing distance of antenna Fig...

Страница 115: ...RK3288 Hardware Design Guide Fig 25 3...

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