RME Audio ADI-2 DAC, Руководство пользователя

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User’s Guide ADI-2 DAC © RME 53
31.2 Emphasis
In the early times of digital audio, with AD and DA converters of only 14 bit resolution, a tech-
nique was used that is also known from radio transmission: pre- and de-emphasis. The audio
signal is equalized to have treble boosted before the conversion. When played back an analog
treble filter (the term high cut seems a bit strong) is required. Overall the audible noise and dis-
tortion caused by the AD and DA conversion was hoped to be reduced this way.
Some older CDs were recorded with Emphasis, and indeed Emphasis is part of the Red Book
standard. Listening to them requires a filter on the playback side or their sound will seem too
bright. The playback of older digital recordings from tape might also require de-emphasis, and
even one of the first DAT recorders used Emphasis constantly.
Fortunately digital to analog converter chips have support for de-emphasis included. The ADI-2
DAC activates the DAC’s de-emphasis automatically when the current source is AES or SPDIF
and the Emphasis bit is set in the incoming Channel Status. The State Overview screen can be
used to track this state, a WARNING SPDIF EMPHASIS message will be shown.
Why warning? Because when using the ADI-2 DAC as audio interface to record SPDIF into an
audio file, the emphasis state is lost. Similarly there exists no mechanism to let the audio play-
back software control the emphasis state of the ADI-2 DAC’s DAC during playback of that re-
corded file. An option
De-emphasis On
in the channel’s I/O menu allows for a manual activation
in such a case.
31.3 SteadyClock FS
RME’s SteadyClock technology guarantees an excellent performance in all clock modes. Its
highly efficient jitter suppression refreshes and cleans up any clock signal.
Usually a clock section consists of an analog PLL for external synchronization and several
quartz oscillators for internal synchronization. SteadyClock requires one quartz only, using a
frequency not equalling digital audio. Modern circuit designs like hi-speed digital synthesizer,
digital PLL, 1 GHz sample rate and analog filtering allow RME to realize a completely newly
developed clock technology, right within the FPGA at lowest costs. The clock's performance
exceeds even professional expectations. Despite its remarkable features, SteadyClock reacts
quite fast compared to other techniques. It locks in fractions of a second to the input signal,
follows even extreme varipitch changes with phase accuracy, and locks directly within a range
of 28 kHz up to 200 kHz.
The further improved SteadyClock FS technology offers even lower self-jitter, and uses a low
phase noise quartz with jitter in the range of femto seconds. Thanks to the highly efficient jitter
suppression, the AD- and DA-conversion always operates on highest sonic level, being com-
pletely independent from the quality of the incoming clock signal.
SteadyClock has been originally developed to gain a stable and clean clock from the heavily
jittery MADI data signal (the embedded MADI clock suffers from about 80 ns jitter). Using the
input sources of the ADI-2 DAC, SPDIF, ADAT or AES, you'll most probably never experience
such high jitter values. But SteadyClock is not only ready for them, it would handle them just on
the fly.