RT8509A
10
DS8509A-00 November 2013
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Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Nevertheless, this value can be decreased for lower output
current requirement. Another consideration is the voltage
rating of the input capacitor which must be greater than
the maximum input voltage.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
−
T
A
) /
θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and
θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125
°
C. The junction to
ambient thermal resistance,
θ
JA
, is layout dependent. For
WDFN-12L 5x5 packages, the thermal resistance,
θ
JA
, is
29.5
°
C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at T
A
= 25
°
C
can be calculated by the following formula :
P
D(MAX)
= (125
°
C
−
25
°
C) / (29.5
°
C/W) = 3.38W for
WDFN-12L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance,
θ
JA
. The derating curve in Figure 2 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 2. Derating Curve of Maximum Power Dissipation
Layout Considerations
For high frequency switching power supplies, the PCB
layout is important to get good regulation, high efficiency
and stability. The following descriptions are the guidelines
for better PCB layout.
For good regulation, place the power components as
close as possible. The traces should be wide and short
enough especially for the high current output loop.
The feedback voltage divider resistors must be near the
feedback pin. The divider center trace must be shorter
and the trace must be kept away from any switching
nodes.
The compensation circuit should be kept away from the
power loops and be shielded with a ground trace to
prevent any noise coupling.
Minimize the size of the LX node and keep it wide and
shorter. Keep the LX node away from the FB.
The exposed pad of the chip should be connected to a
strong ground plane for maximum thermal consideration.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
25
50
75
100
125
Ambient Temperature (°C)
M
a
xi
m
u
m
P
o
w
e
r D
is
si
p
a
tio
n
(W
)
1
Four-Layer PCB
