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DS8241-03 January 2014
www.richtek.com
RT8241
©
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
to rise, eventually hitting the over voltage protection
threshold and shutting down the device. If the device hits
the negative over current threshold again before output
voltage is discharged to the target level, the low side
MOSFET is turned off and the process repeats. It ensures
maximum allowable discharge capability when output
voltage continues to rise. On the other hand, if the output
is discharged to the target level before negative current
threshold is reached, the low side MOSFET is turned off,
the high side MOSFET is then turned on, and the device
resumes normal operation.
MOSFET Gate Driver (UGATE, LGATE)
The high side driver is designed to drive high current, low
R
DS(ON)
N-MOSFET(s). When configured as a floating
driver, 5V bias voltage is delivered from the V
CC
supply.
The average drive current is proportional to the gate charge
at V
GS
= 5V times switching frequency. The instantaneous
drive current is supplied by the flying capacitor between
the BOOT and PHASE pins. A dead time to prevent shoot
through is internally generated between high side
MOSFET off to low side MOSFET on, and low side
MOSFET off to high side MOSFET on. The low side driver
is designed to drive high current, low R
DS(ON)
N-
MOSFET(s). The internal pull-down transistor that drives
LGATE low is robust, with a 0.8
Ω
typical on resistance. A
5V bias voltage is delivered from the V
CC
supply. The
instantaneous drive current is supplied by the flying
capacitor between VCC and GND.
For high current applications, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate drain coupling, which can lead to
efficiency killing, EMI-producing shoot through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time, as shown in
Figure 7.
Figure 7. Reducing the UGATE Rise Time
PHASE
UGATE
Q1
C
IN
V
IN
BOOT
R
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull-up resistor. When the feedback voltage is above
1.1V or below 0.45V, PGOOD will be pulled low. PGOOD
is allowed to be high until soft-start ends and the output
reaches 89% of its set voltage. There is a 2.5
μ
s delay
built into PGOOD circuitry to prevent false transition.
When Gx changes, PGOOD remains in its present state
for 32 clock cycles. Meanwhile, V
OUT
or V
FB
regulates to
the new level.
POR, UVLO and Soft-Start
Power On Reset (POR) occurs when VCC rises above
3.7V (typ.). After POR is triggered, the RT8241 will reset
the fault latch and prepare the PWM for operation. Below
3.6V (typ.), the VCC Under Voltage Lockout (UVLO)
circuitry inhibits switching by keeping UGATE and LGATE
low. A built-in soft-start is used to prevent surge current
from the power supply input after EN is enabled. It clamps
the ramping of the internal reference voltage which is
compared with the FB signal. The typical soft-start duration
is 0.8ms.
Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When V
FB
exceeds 1.1V, over voltage
protection is triggered and the low side MOSFET is latched
on. This activates the low side MOSFET to discharge the
output capacitor. The RT8241 is latched once OVP is
triggered and can only be released by VCC or EN power
on reset. There is a 5
μ
s delay built into the over voltage
protection circuit to prevent false transitions.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When V
FB
is less than 0.45V, under
voltage protection is triggered and then both UGATE and
LGATE gate drivers are forced low. In order to remove the
residual charge on the output capacitor during the under
voltage period, if PHASE is greater than 1V, the LGATE
is forced high until PHASE is lower than 1V. There is a
3.5
μ
s delay built into the under voltage protection circuit
to prevent false transitions. During soft-start, the UVP
blanking time is 3ms.
