RT7297B
11
DS7297B-02 September 2012
www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
OUT
IN
RMS
OUT(MAX)
IN
OUT
V
V
I
= I
1
V
V
−
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
approximate RMS current is given :
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/ 2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required. Several
capacitors may also be paralleled to meet size or height
requirements in the design. For the input capacitor, two
10
μ
F low ESR ceramic capacitors are suggested. For the
suggested
capacitor, please refer to Table 3 for more details. The
selection of C
OUT
is determined by the required ESR to
minimize voltage ripple. Moreover, the amount of bulk
capacitance is also a key for C
OUT
selection to ensure
that the control loop is stable. Loop stability can be
checked by viewing the load transient response as
described in a later section.
The output ripple,
Δ
V
OUT
, is determined by :
OUT
L
OUT
1
V
I
ESR
8fC
⎡
⎤
Δ
≤ Δ
+
⎢
⎥
⎣
⎦
The output ripple will be the highest at the maximum input
voltage since
Δ
I
L
increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, V
IN
. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
V
IN
large enough to damage the part.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125
°
C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= (T
J(MAX)
−
T
A
) /
θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature , T
A
is the ambient temperature and the
θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT7297B, the maximum junction temperature is 125
°
C.
The junction to ambient thermal resistance
θ
JA
is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance
θ
JA
is 75
°
C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at T
A
= 25
°
C can be calculated by following
formula :
P
D(MAX)
= (125
°
C
−
25
°
C) / (75
°
C/W) = 1.333W
(min.copper area PCB layout)
P
D(MAX)
= (125
°
C
−
25
°
C) / (49
°
C/W) = 2.04W
(70mm
2
copper area PCB layout)
The thermal resistance
θ
JA
of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance
θ
JA
can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
As shown in Figure 7, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 7.a),
θ
JA
is 75
°
C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 7.b) reduces the
θ
JA
to 64
°
C/W. Even further,
increasing the copper area of pad to 70mm
2
(Figure 7.e)
reduces the
θ
JA
to 49
°
C/W.
