32
Table 2.10 Measurement Item (cont)
Selected Name
Option
Non-cacheable area data access cycle
NCD
Cacheable area access cycle
CC
Cacheable area instruction access cycle
CIC
Cacheable area data access cycle
CDC
Access counts other than instruction/data
NAM
Non-cacheable area access counts
NCN
Non-cacheable area instruction access counts
NCIN
Non-cacheable area data access counts
NCDN
Cacheable area access counts
CN
Cacheable area instruction access counts
CIN
Cacheable area data access counts
CDN
Each measurement condition is also counted when conditions in table 2.11 are generated.
Table 2.11 Performance Measurement Conditions to be Counted
Measurement Condition
Notes
No caching due to the
settings of TLB cacheable
bit
Counted for accessing the cacheable area.
Cache-on counting
Accessing the non-cacheable area is counted less than the actual
number of cycles and counts. Accessing the cacheable, X/Y-RAM,
and U-RAM areas is counted more than the actual number of cycles
and counts.
Branch count
The counter value is incremented by 2. This means that two cycles
are valid for one branch.
Notes: 1. In the non-realtime trace mode of the AUD trace, normal counting cannot be performed
because the generation state of the stall or the execution cycle is changed.
2. Since the clock source of the counter is the CPU clock, counting also stops when the
clock halts in the sleep mode.
2. Displaying the measured result
The measured result is displayed in the [Performance Analysis] window or the
PERFORMANCE_ANALYSIS command with hexadecimal (32 bits).
