Renesas Starter Kit+ for RX72N
5. User Circuitry
R20UT4443EG0100 Rev. 1.00
Page 22 of 57
Nov 30, 19
5.9
Ethernet
When running any Ethernet software, a unique MAC address should be used. A unique Renesas allocated MAC
address is attached to the PCB as a sticker, and should be always be used with this device ensured to ensure full
compatibility when using other Renesas hardware on a common Ethernet connection.
An Ethernet controller IC is fitted to the CPU board, and is connected to the Ethernet MCU peripheral. The
RX72N MCU supports full duplex 10Mb/s and 100Mb/s transmission and reception. Refer to §5.4 for
information about the Ethernet LEDs. The connections for the Ethernet controller are listed in
below.
Table 5-9: Ethernet Connections
Ethernet signal
Function
MCU
Port
Pin
ET1-TXCLK
MII: Transmit clock
PN2
G9
ET1-TXEN_RMII1TXDEN
MII/RMII: Transmit data valid
PQ7
H8
ET1-ETXD0_RMII1TXD0
MII/RMII: Transmit data 0
PQ5
E10
ET1-ETXD1_RMII1TXD1
MII/RMII: Transmit data 1
PQ6
F9
ET1-ETXD2
MII: Transmit data 2
PN0
E6
ET1-ETXD3
MII: Transmit data 3
PN1
F8
ET1-RXCLK
MII: Receive clock
RMII: Reference clock
*1
PQ4
E11
ET1-RXER_RMII1RXER
MII/RMII: Receive error
PN3
H9
ET1-ERXD0_RMII1RXD0
MII/RMII: Receive data 0
P94
B7
ET1-ERXD1_RMII1RXD1
MII/RMII: Receive data 1
P95
B8
ET1-ERXD2
MII: Receive data 2
P96
A8
ET1-ERXD3
MII: Receive data 3
P97
C9
ET1-COL
MII: Collision detect signal
P91
B5
ET1-CRS
MII: Carrier sense
PQ0
E7
ET1-LED0
MII/RMII: Link status input from the PHY-LSI
P93
D7
ET1-RXDV_RMII1CRSDV
MII: Receive data valid
P90
C6
RMII: Carrier sense/receive data valid
*1
PQ0
E7
*1
: This connection is a not available in the default RSK+ configuration - refer to §6 for the required
modifications.
Table 5-10: Ethernet Connections
Ethernet signal
Function
MCU
Port
Pin
CLKOUT25M
MII: For PHY clock 25MHz
PH7
K1
ET-MDIO
MII/RMII: Management data I/O
P30
J5
ET-MDC
MII/RMII: Management data clock
P31
J4
SW-PHYRESn
*1
MII/RMII: PHY reset controlled by the reset switch on the board
-
-
ET-GPIORST
*1
MII/RMII: PHY reset controlled by RX72N port PL4
PL4
R12
ET-INTn
MII/RMII: PHY Interrupt
P15
J7
*1
: In the default RSK+ configuration, both the SW-PHYRESn and ET-GPIORST lines are connected to the
reset pin of the Ethernet controller IC. Normally, reset is activated by SW-PHYRESn, so set port PL4 (ET-
GPIORST) of the RX72N in the input direction. Refer to §6 for using ET-GPIORST as a reset.
Table 5-11: Default PHY setting
Default PHY setting items
Default PHY setting contents
PHY Address
ETHERNET (U13)=1
MII/RMII
MII
Isolate
Disable
Speed
100Mbps
Duplex
Full-Duplex
Auto negotiation
Enable
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