Renesas RL78/G23, Руководство пользователя

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RL78/G23 ELCL Multiple Parameter Monitoring Function
R01AN5615EJ0200 Rev.2.00 Page 34 of 42
Mar.24.22
Table 5-9 ELCL register settings (Logic cell block L2)
Register
Symbol Register Name Setting Description
ELL2SEL0 Event link L2 signal select
register 0 07H Select the signal selected by ELISEL6 as the link
target of L2
ELL2SEL1 Event link L2 signal select
register 1 0DH Output signal 0 in logic cell block L1 is selected
as the link target of L2
ELL2SEL2 Event link L2 signal select
register 2 0EH Output signal 1 in logic cell block L1 is selected
as the link target of L2
ELL2SEL4 Event link L2 signal select
register 4 03H Select the signal selected by ELISEL8 as the link
target of L2
ELL2SEL6 Event link L2 signal select
register 6 00H No selection (fixed to 0)
ELL2LNK0 Event link L2 output select
register 0 0AH Link target selected by ELL2SEL0 to set control
of flip-flop 0 in logic cell block L2
ELL2LNK1 Event link L2 output select
register 1 01H Link target selected by ELL2SEL1 to input 0 of
logic cell 0 in logic cell block L2
ELL2LNK2 Event link L2 output select
register 2 02H Link target selected by ELL2SEL2 to input 1 of
logic cell 0 in logic cell block L2
ELL2LNK4 Event link L2 output select
register 4 01H Link target selected by ELL2SEL4 to set control
of flip-flop 1 in logic cell block L2
ELL2LNK6 Event link L2 output select
register 6 03H Link target selected by ELL2SEL6 to clock of flip-
flop 0 and 1 in logic cell block L2
ELL2CTL Logic cell block L2 control
register C2H Enable use of logic cell block L2 flip-flops 0 and 1,
logic cell 0 selects OR circuit
Figure 5-7 Setting of logic cells L2
L2L0
ELL2SEL0
ELL2SEL1
ELL2SELn
ELISEL6
ELISEL8
ELL2LNKn ELL2CTL
L2F0
L2F1
L1L0 Output Signal
L1L1 Output Signal
ELL2SEL2
ELL2SEL4
ELL2SEL6
L2L0 Output Signal
L2F0 Output Signal
L2F1 Output Signal