Renesas QB-RL78L1C, Руководство пользователя

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QB-RL78L1C In-Circuit Emulator CHAPTER 4 CAUTIONS
R20UT2703EJ0200 Rev.2.00 Page 35 of 42
Jan 31, 2014
- The detection voltage value of the voltage detector (LVD)
LVD detection voltage differs from that of the target device.
.
Table 4-5. The detection voltage
Target device RL78/L1C Target device RL78/L13 QB-RL78L1C
Rising edge Failing edge Rising edge Failing edge Rising edge Failing edge
1.67V 1.63V 1.67V 1.63V 1.64V
1.77V 1.73V 1.77V 1.73V 1.74V
1.88V 1.84V 1.88V 1.84V 1.85V
1.98V 1.94V 1.98V 1.94V 1.95V
2.09V 2.04V 2.09V 2.04V 2.05V
2.50V 2.45V 2.50V 2.45V 2.46V
2.61V 2.55V 2.61V 2.55V 2.56V
2.71V 2.65V 2.71V 2.65V 2.66V
2.81V 2.75V 2.81V 2.75V 2.76V
2.92V 2.86V 2.92V 2.86V 2.87V
3.02V 2.96V 3.02V 2.96V 2.97V
3.13V 3.06V 3.13V 3.06V 3.07V
－ －
3.75V 3.67V 3.68V
－ －
4.06V 3.98V 3.99V
- I/O port output signal level detection function
I/O port output signal level detection function emulation is not supported.
Even if you set as “Output data is read (PMS0=1)” at port mode select register (PMS), the value of the port
register (Pmn) is read.
Remark m = 0 to 8, 12, 14, 15, n = 0 to 7
- PLL clock (RL78/L1C only)
If there is mismatch on the High-speed system clock frequency (f
MX
) setting and the PLL operation register
(DSCCTL) setting, QB-RL78L1C generates 1MHz as PLL oscillation frequency (f
PLL
).
Refer to the device user’s manual regarding a High-speed system clock frequency for USB clock and register
setting of PLL.