Renesas QB-RL78L1C, Руководство пользователя

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QB-RL78L1C In-Circuit Emulator CHAPTER 4 CAUTIONS
R20UT2703EJ0200 Rev.2.00 Page 34 of 42
Jan 31, 2014
- UREGC pin voltage levels (RL78/L1C only)
UREGC pin voltage level on QB-RL78L1C differs from the target device.
Target device: 3.3V
QB-RL78L1C: Open
- TTL input buffer characteristics
If the port input mode register (PIM) is used to set the input of a pin that can be set for the TTL buffer to the TTL
level, the high-level input voltage characteristics differs from that of the target device.
Refer to a device user’s manual about the pins which setting is possible to a TTL buffer.
Table 4-4. Input Characteristics of TTL
Item Conditions
Target device
RL78/L1C
VIH MIN
2.0V
（
3.3 V
≤
VDD
≤
3.6 V
）
1.5V
（
1.6 V
≤
VDD < 3.3 V
）
VIL MAX
0.5V
（
3.3 V
≤
VDD
≤
3.6 V
）
0.32V
（
1.6 V
≤
VDD < 3.3 V
）
Target device
RL78/L13
VIH MIN
2.2V
（
4.0 V
≤
VDD
≤
5.5 V
）
2.0V
（
3.3 V
≤
VDD < 4.0 V
）
1.5V
（
1.6 V
≤
VDD < 3.3 V
）
VIL MAX
0.8V
（
4.0 V
≤
VDD
≤
5.5 V
）
0.5V
（
3.3 V
≤
VDD < 4.0 V
）
0.32V
（
1.6 V
≤
VDD < 3.3 V
）
QB-RL78L1C
VIH MIN
2.0V
（
3.3 V
≤
VDD
≤
5.5 V
）
1.17V
（
1.6 V
≤
VDD < 3.3 V
）
VIL MAX
0.8V
（
3.3 V
≤
VDD
≤
5.5 V
）
0.62V
（
1.6 V
≤
VDD < 3.3 V
）