QB-78F1026
CHAPTER 4 CAUTIONS
R20UT0290JJ0100 Rev. 1.00
Page 28 of 29
Sep 30, 2010
4.1.7
P10 to P12, P15, P60 to P63, P111, P121, and P122 pins
The input characteristics of the P10 to P12, P15, P60 to P63, P111, P121, and P122 pins differ between the target
device and emulator.
Table 4-2. Input Characteristics of P10, P11, and P122 Pins
Item
Input Characteristics of P10, P11, and P122 Pins
Target device
Schmitt input
IECUBE CMOS
input
Table 4-3. Input Characteristics of P12, P15, P60 to P63, and P111 Pins
Item
Input Characteristics of P12, P15, P60 to P63,
and P111 Pins
Target device
CMOS input
IECUBE Schmitt
input
4.1.8 FLMD0
pin
The processing for the FLMD0 pin differs from that of the target device.
Table 4-4. FLMD0 Pin Processing
Item
FLMD0 Pin Processing
Target device
Protection resistance: 4.5 k
Ω
(TYP.)
Pull-up/pull-down resistors: 10 k
Ω
(MIN.), 20 k
Ω
(TYP.), 100 k
Ω
(MAX.)
IECUBE
Protection resistance: 4.7 k
Ω
(TYP.)
Pull-up/pull-down resistors: 29 k
Ω
(MIN.), 30 k
Ω
(TYP.), 32 k
Ω
(MAX.)
4.1.9
Power-on-clear (POC) voltage value
The power-on-clear (POC) voltage value differs from that of the target device.
Table 4-5. Power-on-clear (POC) voltage value
Item MIN.
TYP.
MAX.
VPOR
1.52 V
1.61 V
1.70 V
Target device
VPDR
1.50 V
1.59 V
1.68 V
VPOR
−
1.65 V
−
IECUBE
VPDR
−
1.55 V
−
