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Rev.1.00  2003.05.08 page 6 of 23

M65881AFP

PIN DESCRIPTION

Pin No.

Name

I/O

Output

Current
on 3.3V

Signal Level

1

VddL

Power Supply for Lch PWM Power Stage (3.3V)

2

OUTL1

O

Lch PWM1 Output for Power Stage

3.3V

3

VssL

GND for Lch PWM Power Stage

4

OUTL2

O

Lch PWM2 Output for Power Stage

3.3V

5

XOVdd

Power Supply for Secondary Master Clock Buffer ( 3.3V )

6

XfsoOUT

O

Buffered Output of Secondary Master Clock (1024/512fso)

2mA

3.3V

7

XOVss

GND for Secondary Master Clock Buffer

8

DVdd

Power Supply for Digital Block (1.8V)

9

DVss

GND for Digital Block

10

MCKSEL

I

Secondary Master Clock Selector "L":1024fso, "H":512fso

3.3V

11

SCDT

I

Serial Control • Data Input

3.3V

12

SCSHIFT

I

Serial Control • Shift Clock Input

3.3V

13

SCLATCH

I

Serial Control • Latch Signal Input

3.3V

14

NSPMUTE

I

PWM Duty 50% Mute ( "L": Active )

3.3V

15

INIT

I

Initialize Input ( Power Supply Reset ) ; "L" : Reset, "H" : Release

3.3V

16

LRCK

I

LRCK Input (PCM Signal )

3.3V

17

BCK

I

BCK Input ( PCM Signal )

3.3V

18

DATA

I

DATA Input ( PCM Signal )

3.3V

19

BFVdd

Power Supply for Input/Output 3.3V Buffer

20

BFVss

GND for Input/Output 3.3V Buffer

21

XfsiIN

I

Primary Master Clock Input (256fsi/512fsi )

3.3V

22

FsoCKO

O

Secondary Fso Clock Output

4mA

3.3V

23

FsoI

I

Secondary Fso Clock Input

3.3V

24

SFLAG

O

Asynchronous Flag ( H: Active )

4mA

3.3V

25

TEST2

I

Test2 must be connected to GND

3.3V

26

TEST1

I

Test1 must be connected to GND

3.3V

27

HPOUTR2

O

Rch PWM2 Output for Headphone

3.3V

28

HPVssR

GND for Rch Headphone

29

HPOUTR1

O

Rch PWM1 Output for Headphone

3.3V

30

HPVddR

Power Supply for Rch Headphone ( 3.3V )

31

HPOUTL2

O

Lch PWM2 Output for Headphone

3.3V

32

HPVssL

GND for Lch Headphone

33

HPOUTL1

O

Lch PWM1 Output for Headphone

3.3V

34

HPVddL

Power Supply for Lch Headphone ( 3.3V )

35

XVss

GND for Secondary Master Clock Input Buffer

36

XfsoIN

I

Secondary Master Clock Input (1024fso/512fso)

3.3V

37

XVdd

Power Supply for Secondary Master Clock Buffer ( 3.3V )

38

VssLR

GND for PWM Power Stage

39

OUTR2

O

Rch PWM 2 Output for Power Stage

3.3V

40

VssR

GND for Rch PWM Power Stage

41

OUTR1

O

Rch PWM 1 Output for Power Stage

3.3V

42

VddR

Power Supply for Rch PWM Power Stage ( 3.3V)

Description

Содержание M65881AFP

Страница 1: ...ith Exponential Approximate Curve Correspondence to Output for Headphone SYSTEM BLOCK DIAGRAM APPLICATION DVD Receiver AV Amplifier RECOMMENDED OPERATING CONDITIONS Logic Block 1 8V 10 PWM Buffer Bloc...

Страница 2: ...Vdd SFLAG TEST2 TEST1 HPOUTR2 HPVssR HPOUTR1 HPVddR HPOUTL2 HPVssL HPOUTL1 HPVddL XVss XfsoIN XVdd VssLR OUTR2 OUTR1 VddR 1 8V system OUTL1 BFVss XfsiIN FsoCKO FsoI 3 3V system 3 3V system 3 3V system...

Страница 3: ...UTR2 OUTL2 Sampling Rate Converter Gain Control DATA BCK LRCK S C D T S C S H I F T S C L A T C H 18 17 16 2 41 39 4 I N I T N S P M U T E X f s i I N Clock Generator Primary Clock Generator Secondary...

Страница 4: ...g Temperature 3 6 Operating Frequency PWMVdd 3 0 3 3 Supply Voltage 3 3V system XVdd XOVdd PWM Output for Power Stage Headphone V Parameter Symbol Conditions Min Typ M Unit VIH3 BFVdd 3 0 to 3 6V 0 75...

Страница 5: ...D GND Reference characteristic S N THD N 102dB typ 0 002 typ Conditions Input 1kHz 0dB Full scale sine wave FS Primary clock 44 1kHz Secondary clock 48kHz PWM Output format 1 AC dithering E DC ditheri...

Страница 6: ...Input PCM Signal 3 3V 19 BFVdd Power Supply for Input Output 3 3V Buffer 20 BFVss GND for Input Output 3 3V Buffer 21 XfsiIN I Primary Master Clock Input 256fsi 512fsi 3 3V 22 FsoCKO O Secondary Fso...

Страница 7: ...ing figures LRCK BCK MSB 16 cycle DATA 16bit MSB 16 cycle 1 fsi 1 2fsi 1 4fsi Left Right DATA 24bit MSB MSB 24 cycle 24 cycle MSB DATA 20bit MSB 20 cycle 20 cycle LSB LSB LSB LSB LSB LSB MSB first rig...

Страница 8: ...e and master clock frequency Input signal and primary clock are related to synchronization The primary clock frequency are 512 or 256 times as much as the input signal fsi 32k 44 1k and 48k The primar...

Страница 9: ...SYNC flag Serial Control System2 Mode bit6 rise edge too While re synchronizing SFLAG pin outputs H and data is muted inside In case of using Multiplex for multi channel application and Single for 2ch...

Страница 10: ...Common setting for Power Stage and Headphone Output Muting Reverse Output Pins Function Output Form Selection 1 2 3 4 Select to 16fso 6bit 16fso 5bit 32fso 5bit from operating rate and data bit lengt...

Страница 11: ...function system2 mode bit6 11 TEST1 TEST2 TEST1 and TEST2 pins are test input for factory shipping test of M65881AFP TEST1 and TEST2 pins must be tied to L level on usual operation 12 Power supply and...

Страница 12: ...dd BFVdd Master clock XfsoIN XfsiIN INIT SCDT SCSHIFT SCLATCH Over 5msec 1 Over 0sec 2 Over 2 fso 3 Power ON Power OFF 1 After a power supply and Master clock become to stable INIT pin must be L over...

Страница 13: ...ects by input signal level and limit gain control The limit Value is set by Gain control Mode bit5 6 NSLMT1 2 and System2 Mode bit17 NSOBIT Limit value setting of output for gain control and bit5 6 NS...

Страница 14: ...value setting continuously In case of Gain value setting continuously for example of setting L Rch independently please take the interval time pulse interval time of SCLATCH signal more than 1 fso For...

Страница 15: ...so 10 416 sec step transition term are following From Maximum value 10100b 11111111b to Minimum value 00000b 00000000b 2816T 29 333msec From 0dB value 10000b 10000000b to Minimum value 00000b 0000000b...

Страница 16: ...4 15 16 17 18 19 20 ASYNC1MODE Asynchronous Detection Flag for Primary Side Zero Mute PWM duty50 L 21 22 PWMMODE0 Selection for PWM Output type L 23 PWMMODE1 L 24 PWMHP Phase of HPOUTL1 R1 based on PW...

Страница 17: ...as MCKSEL L in advance is required 2 Serial control system1 mode bit22 23 PWMMODE0 1 H L When a setup of both 1 and 2 is completed it changes to Form2 When 2 is set up before 1 The term until a setup...

Страница 18: ...Secondary master clock 512fso Non dithering L L bit Flag name Functional Explanation H L INIT 1 MODE1 Mode settiing1 H fixed 2 MODE2 Mode setting2 L fixed 3 IMCKSEL Input master clock Selection 512fs...

Страница 19: ...MUTE Fixed PWM duty 50 Mute L Mute release H Mute This function exists also in a pin by the same name This Mute function can be set either NSPMUTE flag or NSPMUTE pin Refer to Page13 about a relation...

Страница 20: ...CLATCH twh twhl twl duty XfsoIN XfiIN twh twhl Item Symbol Condition Min Typ Max Unit XfsoIN Duty Ratio duty XfsoIN 40 50 60 512fsi 30 50 70 256fsi 40 50 60 SCSHIFT Pulse time tw SCSHIFT 160 nsec SCDT...

Страница 21: ...elect L 1024Fso H 512Fso Flag Output Secondary Clock output Oscillator Power Driver Power Driver Initialize Control Mute Control Input Mode Select2 M65881AFP LRCK BCK DATA XfsiIN Primary Clock OUTL1 O...

Страница 22: ...E Plastic 42pin 450mil SSOP Symbol Min Nom Max A A 2 b c D E L L 1 y Dimension in Millimeters H E A 1 I 2 25 0 05 0 13 0 3 17 2 8 63 11 3 0 27 1 0 2 3 0 15 0 5 17 4 8 8 0 93 11 5 0 765 1 43 11 4 2 4 0...

Страница 23: ...n The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from...

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