AN9910 Rev.1.00
Page 2 of 6
June 2001
ISL5217EVAL1
Getting Started
Installation Requirements
1. A personal computer running Windows 95, Windows 98, or
Windows NT with a bidirectional parallel port.
2. A 5V
DC
power supply capable of supporting the evaluation
CCA by sourcing 2.0A.
Software Installation
Windows 95
1. Execute the ‘ISL5217.exe’ installation program from the
distribution media. This program will create folder ISL5217
and install the required files.
2. Select and execute ‘ste51en.exe.’ This program will install
the required Windows scripting host.
Windows 98
1. Execute the ‘ISL5217.exe’ installation program from the
distribution media. This program will create folder ISL5217
and install the required files.
2. If the target computer’s operating system was loaded with
the default system configuration, it is not necessary to
select and execute “ste51en.exe.” This program would
have been part of the default. If scripting errors are
encountered, execute ‘ste51en.exe.’
Windows NT/Windows 2000
1. Execute the ‘ISL5217.exe’ installation program from the
distribution media. This program will create folder ISL5217
and install the required files.
2. Select and execute ‘ste51en.exe.’ This program will install
the required Windows scripting host.
3. Execute ‘Port95nt.exe’ from the disk. ‘Port95nt.exe’ installs
the DriverLINX Port I/O Driver parallel port drivers, a
necessary component for running the software under
Windows NT/2000. In order to run ‘Port95nt.exe’
successfully you must have administrator privileges on your
NT machine. Upon completion, you must reboot in order for
the driver to take effect.
Hardware Description
Board Components
The evaluation board consists of four major components as
depicted in the block diagram:
1. ISL5217 U1: This is the Quad Programmable Upconverter
device. This device is clocked by a user selectable BIT-CLK
or by the onboard programmable skew clock buffer U7’s
CLK2.
2. RAM U2. The board uses a 128K x 32 bits synchronous-
pipelined cache RAM to store digital data patterns for the In-
phase and Quadrature inputs to the ISL5217. The RAM is
clocked with U7’s CLK1. The RAM device memory is
partitioned to allocate separate serial channel A-D input
areas for the ISL5217. Space is also reserved to provide for
dynamic reconfiguration data storage to allow real time re-
configuration of the ISL5217. The RAM can hold I/Q
stimulus patterns that are repeatable with no overhead.
3. CPLD U10: The CPLD’s main function is serve as the
configuration handler between the PC’s parallel port and
the FPGA. The CPLD is factory configured with file
CPLD_217.jed via either the JTAG pins or the parallel port
to support loading the FPGA in selectMAP mode. Upon
initilization of the PUC.exe software, the PC begins
streaming the ISL5217.bit FPGA configuration file
information over the parallel port to the CPDL. The CPLD bit
reverses the data and manages the handshaking and
dataflow into the FPGA until configuration is complete.
Upon the FPGA’s assertion of DONE, the CPLD
three-states and allows direct parallel port access to the
FPGA to begin PUC controlled program execution. The
CPLD and FPGA are in system re-programmable, allowing
for CCA configuration fielded upgrades.
4. FPGA U3: The FPGA is the primary controller on the CCA.
It manages all input pins to the ISL5217 and controls the
RAM interface to provide for I and Q data input into the
ISL5217. It interfaces directly over the parallel port to allow
writing and readback of the ISL5217 configuration registers.
The FPGA is configured upon program initilization, which
provides for fielded upgrades.
Communication with the PC is achieved using the ‘EPP’
(Standard Parallel Port) handshake. The evaluation board’s
main oscillator U6 can be removed, allowing for external
clocking through SMA connector J11. When providing this
clock externally, a 50
terminator for the external clock source
should be enabled through jumper JP6 1-2.
FPGA Registers
The FPGA is configured with 128 registers which contain the
control information for the CCA. The Address register and a
Data register for implementing the EPP handshake, do not
necessarily require an EPP, as the evaluation software will
emulate it. These registers can be accessed from the
evaluation software using the console commands “read” and
“write” or the script commands “PUC.read” and “PUC.write.”
For more details refer to the ‘Software Description’ section.
Hardware Configuration
Verify the following default jumper configurations per Table 1:
1. JP3, JP4, JP5, JP6 and JP7 in 2-3 position.
2. JP9 in 1-2 position.
3. J9-13 to J9-14 jumper installed.
4. JP10-JP13 in position 1-2. This configures the initial board
address to 0000.
5. JP1-JP2, JP8 not installed.
6. Connect the 5 volt power supply to the evaluation board
connector J16 utilizing the supplied power cable. Ensure
the power supply can source 2.0A regulated at 5V
DC
5%.
WARNING: Ensure care is utilized to prevent the
application of reverse polarity power to the CCA.
