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121

BNOT Rn,Rd

B

(Rn8 of Rd8)

←

(Rn8 of Rd8)

2

–

– –

–

–

–

2

BNOT Rn,@Rd

B

(Rn8 of @Rd16)

←

(Rn8 of @Rd16)

4

–

– –

–

–

–

8

BNOT Rn,@aa:8

B

(Rn8 of @aa:8)

←

(Rn8 of @aa:8)

4

–

– –

–

–

–

8

BTST #xx:3,Rd

B

(#xx:3 of Rd8)

→

Z

2

–

– –

◊

–

–

2

BTST #xx:3,@Rd

B

(#xx:3 of @Rd16)

→

Z

4

–

– –

◊

–

–

6

BTST #xx:3,@aa:8

B

(#xx:3 of @aa:8)

→

Z

4

–

– –

◊

–

–

6

BTST Rn,Rd

B

(Rn8 of Rd8)

→

Z

2

–

– –

◊

–

–

2

BTST Rn,@Rd

B

(Rn8 of @Rd16)

→

Z

4

–

– –

◊

–

–

6

BTST Rn,@aa:8

B

(Rn8 of @aa:8)

→

Z

4

–

– –

◊

–

–

6

BLD #xx:3,Rd

B

(#xx:3 of Rd8)

→

C

2

–

– –

–

–

◊

2

BLD #xx:3,@Rd

B

(#xx:3 of @Rd16)

→

C

4

–

– –

–

–

◊

6

BLD #xx:3,@aa:8

B

(#xx:3 of @aa:8)

→

C

4

–

– –

–

–

◊

6

BILD #xx:3,Rd

B

(#xx:3 of Rd8)

→

C

2

–

– –

–

–

◊

2

BILD #xx:3,@Rd

B

(#xx:3 of @Rd16)

→

C

4

–

– –

–

–

◊

6

BILD #xx:3,@aa:8

B

(#xx:3 of @aa:8)

→

C

4

–

– –

–

–

◊

6

BST #xx:3,Rd

B

C

→

(#xx:3 of Rd8)

2

–

– –

–

–

–

2

BST #xx:3,@Rd

B

C

→

(#xx:3 of @Rd16)

4

–

– –

–

–

–

8

BST #xx:3,@aa:8

B

C

→

(#xx:3 of @aa:8)

4

–

– –

–

–

–

8

BIST #xx:3,Rd

B

C

→

(#xx:3 of Rd8)

2

–

– –

–

–

–

2

BIST #xx:3,@Rd

B

C

→

(#xx:3 of @Rd16)

4

–

– –

–

–

–

8

BIST #xx:3,@aa:8

B

C

→

(#xx:3 of @aa:8)

4

–

– –

–

–

–

8

BAND #xx:3,Rd

B

C

∧

(#xx:3 of Rd8)

→

C

2

–

– –

–

–

◊

2

BAND #xx:3,@Rd

B

C

∧

(#xx:3 of @Rd16)

→

C

4

–

– –

–

–

◊

6

BAND #xx:3,@aa:8

B

C

∧

(#xx:3 of @aa:8)

→

C

4

–

– –

–

–

◊

6

BIAND #xx:3,Rd

B

C

∧

(#xx:3 of Rd8)

→

C

2

–

– –

–

–

◊

2

BIAND #xx:3,@Rd

B

C

∧

(#xx:3 of @Rd16)

→

C

4

–

– –

–

–

◊

6

BIAND #xx:3, @aa:8

B

C

∧

(#xx:3 of @aa:8)

→

C

4

–

– –

–

–

◊

6

BOR #xx:3,Rd

B

C

∨

(#xx:3 of Rd8)

→

C

2

–

– –

–

–

◊

2

BOR #xx:3,@Rd

B

C

∨

(#xx:3 of @Rd16)

→

C

4

–

– –

–

–

◊

6

BOR #xx:3, @aa:8

B

C

∨

(#xx:3 of @aa:8)

→

C

4

–

– –

–

–

◊

6

BIOR #xx:3, Rd

B

C

∨

(#xx:3 of Rd8)

→

C

2

–

– –

–

–

◊

2

Addressing mode/
instruction length

Mnemonic

Operation

Condition code

I

H N

Z V C

Appendix B. Instruction Set List (cont.)

S

iz

e

#

x

x

:8

/1

6

R

n

@

R

n

@(d:16,

Rn)

@

-R

n

/@

R

n

+

@

a

a

:8

/1

6

@(d:8,

PC)

@

@

a

a

No.

of

States*

«
...
125
126
127
128
129
...
»

Содержание H8/300 Series

Страница 1: ...mory SRAMs etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technolo...

Страница 2: ...H8 300 Programming Manual...

Страница 3: ...conditionally 44 BCLR Bit CLeaR 47 BIAND Bit Invert AND 49 BILD Bit Invert LoaD 50 BIOR Bit Invert OR 51 BIST Bit Invert STore 52 BIXOR Bit Invert eXclusive OR 53 BLD Bit LoaD 54 BNOT Bit NOT 55 BOR...

Страница 4: ...OR inclusive OR logical 94 ORC inclusive OR Control register 95 POP POP data 96 PUSH PUSH data 97 ROTL ROTate Left 98 ROTR ROTate Right 99 ROTXL ROTate with eXtend carry Left 100 ROTXR ROTate with eX...

Страница 5: ...XORC eXclusive OR Control register 116 Appendix A Operation Code Map 117 Appendix B Instruction Set List 118 Appendix C Number of Execution States 124...

Страница 6: ...teen 8 bit general registers and a concise optimized instruction set This manual gives detailed descriptions of the H8 300 instructions The descriptions apply to all chips in the H8 300 Series Assembl...

Страница 7: ...with a 10MHz system clock Its general registers can be accessed as 16 bit word registers or 8 bit byte registers The instruction set includes both 8 bit and 16 bit instructions Section 1 of this manu...

Страница 8: ...in a byte operand All operational instructions except ADDS and SUBS can operate on byte data Item Description Address space 64K bytes H 0000 to H FFFF Data types Bit 4 bit packed BCD byte word 2 bytes...

Страница 9: ...al registers as shown in figure 1 1 Figure 1 1 Register Data Structure 1 Bit data 1 Bit data Byte data Byte data Word data 4 Bit BCD data Data type Don t care 4 3 7 0 Data format 7 0 7 6 5 4 3 2 1 0 D...

Страница 10: ...ack two identical copies of the CCR are pushed to make a complete word When they are returned the lower byte is ignored 1 1 3 Address Space The H8 300 CPU supports a 64K byte address space The memory...

Страница 11: ...re are two control registers the 16 bit program counter PC and the 8 bit condition code register CCR Figure 1 3 CPU Registers 0 7 R0H R0L R1H R1L R2H R2L R3L R3H R4L R4H R5H R5L R6H R6L R7H R7L SP 0 1...

Страница 12: ...d as a synonym for R7 As indicated in figure 1 4 R7 SP points to the top of the stack Figure 1 4 Stack Pointer 1 2 2 Control Registers The CPU has a 16 bit program counter PC and an 8 bit condition co...

Страница 13: ...icate a nonzero result Bit 1 Overflow V This bit is set to 1 when an arithmetic overflow occurs and cleared to 0 at other times Bit 0 Carry C This bit is used by Add subtract and compare instructions...

Страница 14: ...ctions by type Tables 1 3 to 1 10 briefly describe their functions Section 2 Instruction Set gives detailed descriptions Table 1 2 Instruction Classification POP Rn is equivalent to MOV W SP Rn PUSH R...

Страница 15: ...General register EAd Destination operand EAs Source operand CCR Condition code register N N negative bit of CCR Z Z zero bit of CCR V V overflow bit of CCR C C carry bit of CCR PC Program counter SP...

Страница 16: ...mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for these two modes MOVFPE B EAs Rd Transfers data from memory to a general register in synchro...

Страница 17: ...d 1 Rd Rd 2 Rd SUBS Adds or subtracts immediate data to or from data in a general register The immediate data must be 1 or 2 DAA B Rd decimal adjust Rd DAS Decimal adjusts adjusts to packed BCD an add...

Страница 18: ...al register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Size Operand size B Byte Table 1 6 Shift Instruction...

Страница 19: ...mediate data or the lower three bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit is specified b...

Страница 20: ...ate data BLD B bit No of EAd C Copies a specified bit in a general register or memory to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the...

Страница 21: ...Carry Set Low C 1 BNE 0 1 1 0 Not Equal Z 0 BEQ 0 1 1 1 Equal Z 1 BVC 1 0 0 0 Overflow Clear V 0 BVS 1 0 0 1 Overflow Set V 1 BPL 1 0 1 0 Plus N 0 BMI 1 0 1 1 Minus N 1 BGE 1 1 0 0 Greater or Equal N...

Страница 22: ...B CCR Imm CCR Logically ORs the condition code register with immediate data XORC B CCR Imm CCR Logically exclusive ORs the condition code register with immediate data NOP PC 2 PC Only increments the...

Страница 23: ...output to input Before Execution of BCLR Instruction Execution of BCLR Instruction BCLR 0 P4DDR clear bit 0 in data direction register After Execution of BCLR Instruction Sequence Operation 1 Read Rea...

Страница 24: ...Example 2 BSET is executed to set bit 0 in the port 4 data register P4DR under the following conditions P47 Input pin Low MOS pull up transistor on P46 Input pin High MOS pull up transistor off P45 P...

Страница 25: ...ion bits P47 and P46 are both modified changing the on off settings of the MOS pull up transistors of pins P47 and P46 Programming Solution The switching of the pull ups for P47 and P46 in example 2 c...

Страница 26: ...Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 Pull up On Off Off Off Off Off Off Off RAM0 1 0 0 0 0 0 0 0 P47 P46 P...

Страница 27: ...r Rm Rn or Rn Rm abs aa 8 Rn or Rn aa 8 r aa 16 Rn or abs Rn aa 16 IMM xx 8 Rn xx 16 Rn IMM r MOVFPE MOVTPE abs r m n m m rn n n n n rn rn n m 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0...

Страница 28: ...op r ADDS SUBS INC DEC DAA DAS NEG NOT n 15 8 7 0 op r IMM ADD ADDX SUBX CMP xx 8 r IMM AND OR XOR xx 8 n n 15 8 7 0 op r r AND OR XOR Rm m n 15 8 7 0 op 15 8 7 0 op r SHAL SHAR SHLL SHLR ROTL ROTR R...

Страница 29: ...ST IMM Operand register direct Rn Bit No immediate xx 3 r Operand register indirect Rn IMM Bit No immediate xx 3 abs Operand absolute aa 8 IMM Bit No immediate xx 3 m n m n n m r n n 15 8 7 0 op 15 8...

Страница 30: ...register direct Rn Bit No immediate xx 3 r Operand register indirect Rn IMM Bit No immediate xx 3 abs Operand absolute aa 8 IMM Bit No immediate xx 3 rn n 15 8 7 0 op op 15 8 7 0 op op 15 8 7 0 op 0 0...

Страница 31: ...abs JMP aa 8 disp BSR JSR Rm JSR aa 16 abs abs JSR aa 8 RTS rm m 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 15 8 7 0 op 0 0 0 0 0 0 0 0 Notation op...

Страница 32: ...ctions Figure 1 10 Machine Language Coding of Block Data Transfer Instruction 15 8 7 0 RTE SLEEP NOP r LDC STC Rn IMM ANDC ORC XORC LDC xx 8 n op 15 8 7 0 op 15 8 7 0 op Notation op Operation field rn...

Страница 33: ...t the instruction has a second word bytes 3 and 4 which is added to the contents of the specified general register to obtain the operand address For the MOV W instruction the resulting address must be...

Страница 34: ...contain 16 bit immediate values The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data Some bit manipulation instructions contain 3 bit immediate data xx 3 in the second...

Страница 35: ...essing to identify a bit within the byte The BSET BCLR BNOT and BTST instructions can also use register direct addressing 1 to identify the bit Effective Address Calculation Table 1 12 explains how th...

Страница 36: ...contents and displacement OP reg 7 6 4 3 15 0 7 6 4 3 OP reg 16 bit register contents 15 0 1 or 2 15 0 Register is decremented beforeoperandaccess 16 bit register contents 15 0 15 0 16 bit displaceme...

Страница 37: ...reg regm regn General register op Operation field disp Displacement abs Absolute address IMM Immediate data OP 15 8 7 0 abs H FF 15 8 7 0 Operand address is in range from H FF00 to H FFFF 15 0 OP 15 0...

Страница 38: ...D B xx 8 Rd 8 rd IMM 2 Register direct ADD B Rs Rd 0 8 rs rd 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte Operation Rd EAs Rd Assembly Language For...

Страница 39: ...16 bit immediate data d 8 d 16 8 bit or 16 bit displacement PC Program counter SP Stack pointer CCR Condition code register Z Zero flag in CCR C Carry flag in CCR The result of the operation on the l...

Страница 40: ...he flag bits in the CCR is indicated The following notation is used Symbol Meaning The flag is altered according to the result of the instruction 0 The flag is cleared to 0 The flag is not changed Und...

Страница 41: ...or 0 if the upper byte is used Registers are thus indicated as follows 16 Bit register rs rd or rn Register 0 0 0 R0 0 0 1 R1 1 1 1 R7 Bit Data Access Bit data are accessed as the n th bit of a byte...

Страница 42: ...number of states indicated is the number required when the instruction and any memory operands are located in on chip ROM or RAM If the instruction or an operand is located in external memory or the...

Страница 43: ...Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte Operation Rd EAs Rd Assembly Language Format ADD B EAs Rd Examples ADD B R0H R1H ADD B H 64 R2L Operand Size Byte Condition...

Страница 44: ...3rd byte 4th byte Operation Rd Rs Rd Assembly Language Format ADD W Rs Rd Examples ADD W R0 R1 Operand Size Word Condition Code I Previous value remains unchanged H Set to 1 when there is a carry from...

Страница 45: ...Assembly Language Format ADDS 1 Rd ADDS 2 Rd Examples ADDS 1 R4 ADDS 2 R5 Operand Size Word Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value remain...

Страница 46: ...ADDX H 0A R2H Operand Size Byte Condition Code I Previous value remains unchanged H Set to 1 if there is a carry from bit 3 otherwise cleared to 0 N Set to 1 when the result is negative otherwise clea...

Страница 47: ...direct AND Rs Rd 1 6 rs rd 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte Operation Rd EAs Rd Assembly Language Format AND EAs Rd Examples AND R6H R...

Страница 48: ...til after the next instruction Instruction Formats Immediate ANDC xx 8 CCR 0 6 IMM 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte Operation CCR IMM C...

Страница 49: ...6 0 IMM rd 2 Register indirect BAND xx 3 Rd 7 C 0 rd 0 7 6 0 IMM 0 6 Absolute address BAND xx 3 aa 8 7 E abs 7 6 0 IMM 0 6 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte...

Страница 50: ...n the next page Examples BHI H 42 BEQ H 7E Operand Size Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value remains unchanged Z Previous value remains...

Страница 51: ...S and BLO are synonyms for BRA BRN BCC and BCS respectively Mnemonic cc Field Description Condition Meaning BRA BT 0 0 0 0 Always True Always true BRN BF 0 0 0 1 Never False Never BHI 0 0 1 0 HIgh C Z...

Страница 52: ...ative PC relative PC relative PC relative PC relative PC relative PC relative PC relative 4 4 4 4 4 4 PC relative PC relative PC relative PC relative 4 4 4 4 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d...

Страница 53: ...The condition code flags are not altered Register direct register indirect or absolute addressing xx 3 or Rn Bit No 7 0 0 Byte data in register or memory EAd Operation 0 Bit No of EAd Assembly Languag...

Страница 54: ...D 0 rd 0 7 2 0 IMM 0 8 Absolute address BCLR xx 3 aa 8 7 F abs 7 2 0 IMM 0 8 Register direct BCLR Rn Rd 6 2 rn rd 2 Register indirect BCLR Rn Rd 7 D 0 rd 0 6 2 rn 0 8 Absolute address BCLR Rn aa 8 7...

Страница 55: ...Assembly Language Format BIAND xx 3 EAd Examples BIAND 0 R1H BIAND 2 R5 BIAND 4 H FFDE 8 Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previ...

Страница 56: ...at BILD xx 3 EAd Examples BILD 3 R4L BILD 5 R5 BILD 7 H FFA2 8 Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value remains unchanged...

Страница 57: ...er or memory EAd 7 0 C C Invert Register direct BIOR xx 3 Rd 7 4 1 IMM rd 2 Register indirect BIOR xx 3 Rd 7 C 0 rd 0 7 4 1 IMM 0 6 Absolute address BIOR xx 3 aa 8 7 E abs 7 4 1 IMM 0 6 Addressing mod...

Страница 58: ...mory EAd Operation C Bit No of EAd Assembly Language Format BIST xx 3 EAd Examples BIST 0 R0L BIST 6 R3 BIST 7 H FFBB 8 Operand Size Byte Condition Code I Previous value remains unchanged H Previous v...

Страница 59: ...or memory EAd 7 0 C C xx 3 Invert Register direct BIXOR xx 3 Rd 7 5 1 IMM rd 2 Register indirect BIXOR xx 3 Rd 7 C 0 rd 0 7 5 1 IMM 0 6 Absolute address BIXOR xx 3 aa 8 7 E abs 7 5 1 IMM 0 6 Addressin...

Страница 60: ...ory EAd Operation Bit No of EAd C Assembly Language Format BLD xx 3 EAd Examples BLD 1 R3H BLD 2 R2 BLD 4 H FF90 8 Operand Size Byte Condition Code I Previous value remains unchanged H Previous value...

Страница 61: ...not altered Register direct register indirect or absolute addressing xx 3 or Rn Bit No 7 0 Invert Byte data in register or memory EAd Operation Bit No of EAd Bit No of EAd Assembly Language Format BNO...

Страница 62: ...D 0 rd 0 7 1 0 IMM 0 8 Absolute address BNOT xx 3 aa 8 7 F abs 7 1 0 IMM 0 8 Register direct BNOT Rn Rd 6 1 rn rd 2 Register indirect BNOT Rn Rd 7 D 0 rd 0 6 1 rn 0 8 Absolute address BNOT Rn aa 8 7 F...

Страница 63: ...the specified bit is not changed Register direct register indirect or absolute addressing Operation C Bit No of EAd C Assembly Language Format BOR xx 3 EAd Examples BOR 5 R2H BOR 4 R1 BOR 5 H FFB6 8 O...

Страница 64: ...gister direct BOR xx 3 Rd 7 4 0 IMM rd 2 Register indirect BOR xx 3 Rd 7 C 0 rd 0 7 4 0 IMM 0 6 Absolute address BOR xx 3 aa 8 7 E abs 7 4 0 IMM 0 6 Addressing mode Mnem Operands 1st byte Instruction...

Страница 65: ...e condition code flags are not altered Register direct register indirect or absolute addressing Operation 1 Bit No of EAd Assembly Language Format BSET xx 3 EAd BSET Rn EAd Examples BSET 3 R2L BSET R2...

Страница 66: ...7 D 0 rd 0 7 0 0 IMM 0 8 Absolute address BSET xx 3 aa 8 7 F abs 7 0 0 IMM 0 8 Register direct BSET Rn Rd 6 0 rn rd 2 Register indirect BSET Rn Rd 7 D 0 rd 0 6 0 rn 0 8 Absolute address BSET Rn aa 8...

Страница 67: ...The possible branching range is 126 to 128 bytes from the address of the BSR instruction Instruction Formats Operation PC SP PC d 8 PC Assembly Language Format BSR d 8 Examples BSR H 76 Operand Size C...

Страница 68: ...BST 2 R3 BST 6 H FFD1 8 Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value remains unchanged Z Previous value remains unchanged V...

Страница 69: ...not altered Register direct register indirect or absolute addressing Operation Bit No of EAd Z Assembly Language Format BTST xx 3 EAd BTST Rn EAd Examples BTST 4 R6L BTST R1H R5 BTST 7 H FF6C 8 Opera...

Страница 70: ...C 0 rd 0 7 3 0 IMM 0 6 Absolute address BTST xx 3 aa 8 7 E abs 7 3 0 IMM 0 6 Register direct BTST Rn Rd 6 3 rn rd 2 Register indirect BTST Rn Rd 7 C 0 rd 0 6 3 rn 0 6 Absolute address BTST Rn aa 8 7...

Страница 71: ...he specified bit is not changed Register direct register indirect or absolute addressing Operation C Bit No of EAd C Assembly Language Format BXOR xx 3 EAd Examples BXOR 4 R6H BXOR 2 R0 BXOR 1 H FFA0...

Страница 72: ...ister direct BXOR xx 3 Rd 7 5 0 IMM rd 2 Register indirect BXOR xx 3 Rd 7 C 0 rd 0 7 5 0 IMM 0 6 Absolute address BXOR xx 3 aa 8 7 E abs 7 5 0 IMM 0 6 Addressing mode Mnem Operands 1st byte Instructio...

Страница 73: ...yte Instruction code No of states 2nd byte 3rd byte 4th byte 67 Operation Rd EAs set condition code Assembly Language Format CMP B EAs Rd Examples CMP B H E5 R1H CMP B R3L R4L Operand Size Byte Condit...

Страница 74: ...of states 2nd byte 3rd byte 4th byte Operation Rd Rs set condition code Assembly Language Format CMP W Rs Rd Examples CMP W R5 R6 Operand Size Word Condition Code I Previous value remains unchanged H...

Страница 75: ...peration Rd decimal adjust Rd Assembly Language Format DAA Rd Examples DAA R5L Operand Size Byte Condition Code I Previous value remains unchanged H Unpredictable N Set to 1 if the adjusted result is...

Страница 76: ...DAA Decimal Adjust Add DAA Instruction Formats Register direct DAA Rd 0 F 0 rd 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte 70...

Страница 77: ...truction is executed under conditions other than those stated above Operation Rd decimal adjust Rd Assembly Language Format DAS Rd Examples DAS R0H Operand Size Byte Condition Code I Previous value re...

Страница 78: ...DAS Decimal Adjust Subtract DAS Instruction Formats Register direct DAS Rd 1 F 0 rd 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte 72...

Страница 79: ...I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the result is negative otherwise cleared to 0 Z Set to 1 if the result is zero otherwise cleared to 0 V Set to 1 if...

Страница 80: ...be avoided by the coding shown on the next page Instruction Formats Operation Rd Rs Rd Assembly Language Format DIVXU Rs Rd Examples DIVXU R0L R1 Operand Size Byte Condition Code I Previous value rem...

Страница 81: ...han 8 bits Overflows can be avoided by using a subprogram like the following A work register is required R0L Divisor R1 Dividend R1 Remainder Quotient 1 R1 R2 H 00 Dividend High 2 R1 Partialremainder...

Страница 82: ...0 R5 and R6 contain the last transfer address 1 Chips in the H8 300 Series having large on chip EEPROM memories use this instruction to write data in the EEPROM For details see the hardware manual for...

Страница 83: ...ves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6 2 When setting R4L and R6 make sure that the final destination address R6 R4L does not exceed H...

Страница 84: ...I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the result is negative otherwise cleared to 0 Z Set to 1 if the result is zero otherwise cleared to 0 V Set to 1 if...

Страница 85: ...JMP aa 8 5 B abs 8 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte 79 Operation EAd PC Assembly Language Format JMP EA Examples JMP R6 JMP H 2000 JMP H...

Страница 86: ...PC Assembly Language Format JSR EA Examples JSR R3 JSR H 1D26 JSR H F0 Operand Size Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value remains unchan...

Страница 87: ...upt NMI are deferred until after the next instruction Instruction Formats Operation EAs CCR Assembly Language Format LDC EAs CCR Examples LDC H 80 CCR LDC R4H CCR Operand Size Byte Condition Code I Lo...

Страница 88: ...Rd Examples MOV B R1L R2H Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the data value is negative otherwise cleared to 0 Z Set...

Страница 89: ...Examples MOV W R3 R4 Operand Size Word Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the data value is negative otherwise cleared to 0 Z Set to 1 i...

Страница 90: ...H MOV B R5 R0L MOV B H FFF1 R1H MOV B H A5 R3L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the data value is negative otherwise...

Страница 91: ...d 16 Rs Rd 6 F 0 rs 0 rd disp 6 Register indirect with post increment MOV W Rs Rd 6 D 0 rs 0 rd 6 Absolute address MOV W aa 16 Rd 6 B 0 0 rd abs 6 Addressing mode Mnem Operands 1st byte Instruction c...

Страница 92: ...nguage Format MOV B Rs EAd Examples MOV B R1L R0 MOV B R3H H 8001 R0 MOV B R5H R4 MOV B R6L H FE77 Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchange...

Страница 93: ...OV W R2 H 0030 R5 MOV W R1 R7 MOV W R0 H FED6 Operand Size Word Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the data value is negative otherwise...

Страница 94: ...located in on chip memory or the on chip register field the MOVFPE instruction is identical in operation to MOV B aa 16 Rd Note that only 16 bit absolute addressing can be used and word data cannot b...

Страница 95: ...located in on chip memory or the on chip register field the MOVTPE instruction is identical in operation to MOV B Rs aa 16 Note that only 16 bit absolute addressing can be used and word data cannot be...

Страница 96: ...is shown schematically below The multiplier can occupy either the upper or lower byte of the source register Instruction Formats Operation Rd Rs Rd Assembly Language Format MULXU Rs Rd Examples MULXU...

Страница 97: ...revious value remains unchanged H Set to 1 when there is a borrow from bit 3 otherwise cleared to 0 N Set to 1 when the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero oth...

Страница 98: ...ronization Instruction Formats NOP 0 0 0 0 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte 92 Operation PC 2 PC Assembly Language Format NOP Examples...

Страница 99: ...NOT Rd Examples NOT R4L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the result is negative otherwise cleared to 0 Z Set to 1 if...

Страница 100: ...Format OR EAs Rd Examples OR R2H R3H OR H C0 R0H Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 when the result is negative otherwise...

Страница 101: ...rred until after the next instruction Instruction Formats Operation CCR IMM CCR Assembly Language Format ORC xx 8 CCR Examples ORC H 80 CCR Operand Size Byte Condition Code I ORed with bit 7 of the im...

Страница 102: ...embly Language Format POP Rn Examples POP R1 Operand Size Word Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the data value is negative otherwise c...

Страница 103: ...n 6 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte Operation Rn SP Assembly Language Format PUSH Rn Examples PUSH R2 Operand Size Word Condition Code I...

Страница 104: ...Assembly Language Format ROTL Rd Examples ROTL R2L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the result is negative otherwis...

Страница 105: ...Rd Assembly Language Format ROTR Rd Examples ROTR R5L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the result is negative otherw...

Страница 106: ...Operation Rd rotated with carry left Rd Assembly Language Format ROTXL Rd Examples ROTXL R1H Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Se...

Страница 107: ...n Rd rotated with carry right Rd Assembly Language Format ROTXR Rd Examples ROTXR R5L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1...

Страница 108: ...is one byte in size but it is popped from the stack as a word in which the lower 8 bits are ignored This instruction therefore adds 4 to the value of the stack pointer R7 Instruction Formats Operation...

Страница 109: ...struction are lost Instruction Formats Operation SP PC Assembly Language Format RTS Examples RTS Operand Size Condition Code I Previous value remains unchanged H Previous value remains unchanged N Pre...

Страница 110: ...Operation Rd shifted arithmetic left Rd Assembly Language Format SHAL Rd Examples SHAL R5H Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set...

Страница 111: ...d shifted arithmetic right Rd Assembly Language Format SHAR Rd Examples SHAR R5H Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if th...

Страница 112: ...nstruction Formats Operation Rd shifted logical left Rd Assembly Language Format SHLL Rd Examples SHLL R2L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains...

Страница 113: ...ht Rd Assembly Language Format SHLR Rd Examples SHLR R3L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 if the result is negative oth...

Страница 114: ...be released only by a nonmaskable interrupt NMI or reset For information about the power down modes see the Hardware Manual for the particular chip Instruction Formats Operation Program execution sta...

Страница 115: ...age Format STC CCR Rd Examples STC CCR R6H Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value remains unchanged Z Previous value re...

Страница 116: ...can also be used to subtract nonzero immediate data 1 ORC H 05 CCR 2 ADD 0 Imm Rd SUBX Imm 1 Rd XORC H 01 CCR Operation Rd Rs Rd Assembly Language Format SUB B Rs Rd Examples SUB B R0L R2L Operand Si...

Страница 117: ...SUB SUBtract binary byte SUB Instruction Formats Register direct SUB B Rs Rd 1 8 rs rd 2 Addressing mode Mnem Operands 1st byte Instruction code No of states 2nd byte 3rd byte 4th byte 111...

Страница 118: ...tates 2nd byte 3rd byte 4th byte Operation Rd Rs Rd Assembly Language Format SUB W Rs Rd Examples SUB W R0 R1 Operand Size Word Condition Code I Previous value remains unchanged H Set to 1 when there...

Страница 119: ...2 Rd Assembly Language Format SUBS 1 Rd SUBS 2 Rd Examples SUBS 1 R3 SUBS 2 R5 Operand Size Word Condition Code I Previous value remains unchanged H Previous value remains unchanged N Previous value...

Страница 120: ...5H Operand Size Byte Condition Code I Previous value remains unchanged H Set to 1 if there is a borrow from bit 3 otherwise cleared to 0 N Set to 1 when the result is negative otherwise cleared to 0 Z...

Страница 121: ...ge Format XOR EAs Rd Examples XOR R0H R1H XOR H F0 R2L Operand Size Byte Condition Code I Previous value remains unchanged H Previous value remains unchanged N Set to 1 when the result is negative oth...

Страница 122: ...next instruction Instruction Formats Operation CCR IMM CCR Assembly Language Format XORC xx 8 CCR Examples XORC H 50 CCR Operand Size Byte Condition Code I Exclusive ORed with bit 7 of the immediate d...

Страница 123: ...S CMP SUBX DAS MOV BRA BRN BHI BLS BCC BCS BNE BEQ BVS BPL BMI BLT BGT BLE MULXU DIVXU RTS BSR RTE JMP JSR BVC BGE BSET BNOT BCLR BTST MOV MOV EEPMOV ADD ADDX CMP SUBX OR XOR AND MOV BXOR BIXOR BAND B...

Страница 124: ...Rd W Rs16 Rd16 2 0 4 MOV W d 16 Rs Rd W d 16 Rs16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 2 0 6 Rs16 2 Rs16 MOV W aa 16 Rd W aa 16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 2 0 4 MOV W Rs d 16 Rd W Rs16 d 16 Rd1...

Страница 125: ...d16 2 2 DEC B Rd B Rd8 1 Rd8 2 2 DAS B Rd B Rd8 decimal adjust Rd8 2 2 NEG B Rd B 0 Rd Rd 2 2 CMP B xx 8 Rd B Rd8 xx 8 2 2 CMP B Rs Rd B Rd8 Rs8 2 2 CMP W Rs Rd W Rd16 Rs16 2 2 MULXU B Rs Rd B Rd8 Rs8...

Страница 126: ...x 3 of Rd8 0 2 2 BCLR xx 3 Rd B xx 3 of Rd16 0 4 8 BCLR xx 3 aa 8 B xx 3 of aa 8 0 4 8 BCLR Rn Rd B Rn8 of Rd8 0 2 2 BCLR Rn Rd B Rn8 of Rd16 0 4 8 BCLR Rn aa 8 B Rn8 of aa 8 0 4 8 BNOT xx 3 Rd B xx 3...

Страница 127: ...d B C xx 3 of Rd8 2 2 BST xx 3 Rd B C xx 3 of Rd16 4 8 BST xx 3 aa 8 B C xx 3 of aa 8 4 8 BIST xx 3 Rd B C xx 3 of Rd8 2 2 BIST xx 3 Rd B C xx 3 of Rd16 4 8 BIST xx 3 aa 8 B C xx 3 of aa 8 4 8 BAND xx...

Страница 128: ...0 2 4 BLS d 8 is true then C Z 1 2 4 BCC d 8 BHS d 8 PC PC d 8 C 0 2 4 BCS d 8 BLO d 8 else next C 1 2 4 BNE d 8 Z 0 2 4 BEQ d 8 Z 1 2 4 BVC d 8 V 0 2 4 BVS d 8 V 1 2 4 BPL d 8 N 0 2 4 BMI d 8 N 1 2...

Страница 129: ...in on chip memory Set to 1 when there is a carry or borrow from bit 11 otherwise cleared to 0 If the result is zero the previous value of the flag is retained otherwise the flag is cleared to 0 Set to...

Страница 130: ...type occurring in each instruction The total number of states required for execution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N S...

Страница 131: ...the MOVFPE and MOVTPE instructions requires 9 to 16 states since it is synchronized with the E clock See the Hardware Manual for timing details Execution Status Access Location instruction cycle On Ch...

Страница 132: ...x 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d...

Страница 133: ...xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2...

Страница 134: ...xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 6 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 1 JMP aa 8 2 1 1 JSR JSR Rn 2...

Страница 135: ...Rs Rd 1 1 MOV W Rs d 16 Rd 2 1 MOV W Rs Rd 1 1 1 MOV W Rs aa 16 2 1 MOVFPE MOVFPE aa 16 Rd 2 1 2 MOVTPE MOVTPE Rs aa 16 2 1 2 MULXU MULXU B Rs Rd 1 6 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B x...

Страница 136: ...BX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 Notes 1 n Initial value in R4L The source and destination operands are accessed n 1 times each 2 Data access requir...

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