Renesas ForgeFPGA, Руководство пользователя

Страница: 4 / 15

ForgeFPGA Configuration Guide
Rev.1.0
May 31, 2022 Page 4
depicts the SPI Mode 0 with CPOL = 0 and CPHA = 0 with the clk idle state = 0 and hence the data is sampled
on rising edge and the shifted on falling edge according to
Table 2.
Figure 3: SPI Mode 0
5. Development Board
There are two pre-requisite steps that need to be performed before the design is sent to the device and can be
further configured with the development board.
a. RTL Synthesis : After creating your desired Verilog Code in the HDL Editor Window of the ForgeFPGA
Workshop, the next step is to create a Netlist of your design. This can be done with the help of the built-
in Synthesis tool that takes input design and produces a Netlist out of it. While performing synthesis, the
input design is analyzed and converted into gate-level representation.
b. Generating Bitstream : To prepare your design to be sent to the device you need to perform the Place-
and-Route procedure, that takes the elements of the synthesized netlist and maps its primitives to FPGA
physical resources. You can do this after successfully generating netlist and pressing Generate
Bitstream button on the control panel. Completing these two steps would have successfully sent the
design to the device.
To enter the debug controls of the development board, we need to select the correct platform on which we need
to configure our device. Under the "Debug" button on the toolbar, select the ForgeFPGA Development Board as
the platform (see
Figure 4 )
Figure 4: ForgeFPGA Development Platform Selection
The FPGA Development Board (see Figure 5 ) is a multi-functional tool that allows the user to develop their
FPGA designs with ease by providing on board power source, digital and analog signal generation, and logic
analysis capabilities. The FPGA Development Board can connect additional external boards called socket
adapters (see
Figure 7 ). The function of the socket adapter board is to implement a stable electrical connection
between the pins of the chip under test and the FPGA Development Board. To implement this, the FPGA
Development Board has a Dual PCIe connector. This connector has 40 differential pairs (80 digital channels), 32
analog pins, service pins, and power pins. Dual PCIe connector is universal and can be applied to multiple
socket adapter boards.