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ForgeFPGA Configuration Guide

 

 

Rev.1.0 
May 31, 2022 

 

Page 5  

 

Driven by the free software, the FPGA Development Board can be configured to work as any one of several 
traditional instruments, which include:  

– 

Logic Analyzer  

– 

Digital pattern generator  

– 

8-channel analog Arbitrary Waveform Generator (AWG)  

– 

Precision ADC  

– 

Three programmable power supplies (+0.6 

V…+3.3 V). The maximum available output current 2 A. 

The same voltage is supplied to the GPIO, for keeping the logic level compatibility with the circuit 
under test. 

Also, the board can be used as an independent unit. The chip can be powered through the EXT PWR connector 
and signals can be read through the through-hole 12-pin connectors (Pmod connectors). 

 

Figure 5: ForgeFPGA Development Board Overview 

To configure the development board and read the desired output, connect the Development Board with the 
Socket Adapter through the PCIe connectors. Put the SLG47910 part in the socket. Then connect the USB cable 
from the laptop to the USB Type-C Connector (see 

Figure 8

). Connect the power cord that was supplied with the 

development board to the power supply connection on the development board. If all the connections are correct, 
then the RED LED( PWR) and BLUE LED(STS) should light up and the software would have recognized the 
SLG47910 part in the socket. 

The user can now either program the chip with the design by clicking on the "Program" button else, the user can 
use the "Emulation" button under the Debugging Controls Panel (see 

Figure 6

) to observe the output and 

manipulate it by connecting the Development Board to Oscilloscope, or any PMOD if required. 

Содержание ForgeFPGA

Страница 1: ...e 7 6 1 Writing the OTP Block 9 6 2 Reading the OTP Block 10 6 3 Read Command Structure 11 7 QSPI Programming Master Mode 11 8 MCU Programming Slave Mode 13 Conclusion 14 9 Revision History 15 1 Terms...

Страница 2: ...der FPGA Core OTP Programmer Configuration Wrapper conf Q D SPI otp_data_rd otp_ctrl op_data_wr ctrl ctrl ctrl tx_data tx_data ctrl tx_data 4 Figure 1 SLG47910 Programming Interface Table 1 Configurat...

Страница 3: ...the polarity of the clock signal during the idle state The idle state is defined as the period when SS is transitioning The CPHA bit selects the clock phase Depending on the CPHA bit the rising or fa...

Страница 4: ...an do this after successfully generating netlist and pressing Generate Bitstream button on the control panel Completing these two steps would have successfully sent the design to the device To enter t...

Страница 5: ...gure 5 ForgeFPGA Development Board Overview To configure the development board and read the desired output connect the Development Board with the Socket Adapter through the PCIe connectors Put the SLG...

Страница 6: ...ForgeFPGA Configuration Guide Rev 1 0 May 31 2022 Page 6 Figure 6 Debugging Controls Panel Figure 7 ForgeFPGA Socket Adapter Top View...

Страница 7: ...A design The OTP memory loads the Configuration RAM The SLG47910 contains three blocks of 4k x 32 bit One Time Programmable OTP Non Volatile Memory NVM which are interfaced via the dedicated SPI Slave...

Страница 8: ...Page 8 Figure 9 SLG47910 Block Diagram The loading of the data through different bitstream sources follow a particular flow and different values of the signal help in determining the mode of operation...

Страница 9: ...g Byte8 bit 6 Reserve bits are indicated by R and the parity bit by P After writing the OTP the write data should be checked using the OTP read command Once the SLG47910 OTP has been written and after...

Страница 10: ...Table 4 Read Write Option Bits Byte 1 0 1 of OTP Packet format Comments 2 b00 Read mode Follows format in Table 5 2 b01 Reserved Not Used 2 b10 Write mode Follows format in Table 3 2 b11 Return Exit...

Страница 11: ...ulated by performing an AND operation of all incoming bytes excluding the parity bit Byte1 Byte2 Byte3 0 6 Table 6 NVM Block Selection NVM Block Selection Address to Read A 18 A 17 A 16 A 15 A 14 A 13...

Страница 12: ...hen issues a final Deep Power down command 0xB9 Figure 14 SPI Read Fast Command Deep Power Down Command The SLG47910 device configures using a single data pin SPI_SI The procedure to enable QSPI Confi...

Страница 13: ...RST signal resetting the array Figure 15 shows the SPI slave timing Figure 15 SPI MCU Mode Timing A 32 bit synchronization word will be inserted in the beginning of the bitstream by the ForgeFPGA Comp...

Страница 14: ...the bitstream is invalid the CONFIG pin will strobe for 1 5us If a load error occurred the Config pin will stay LOW SPI Frequency could be from kHz to MHz Conclusion The three configuration options OT...

Страница 15: ...ForgeFPGA Configuration Guide Rev 1 0 May 31 2022 Page 15 9 Revision History Revision Date Description 1 0 10 Mar 2022 Initial Version...

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