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User Manual
ForgeFPGA Configuration Guide
Rev.1.0
May 31, 2022 Page 1
© 2022 Renesas Electronics
This document describes how to configure the ForgeFPGA core from three different configuration bitstream
sources: External SPI/QSPI Flash, Internal OTP, MCU as a host.
Contents
1. Terms and Definitions ................................................................................................................................... 1
2. References ...................................................................................................................................................... 1
3. Introduction .................................................................................................................................................... 2
4. General SPI Interface ..................................................................................................................................... 2
4.1 SPI Modes with Clock Polarity and Clock Phase .................................................................................. 3
5. Development Board ....................................................................................................................................... 4
6. OTP Read/Write .............................................................................................................................................. 7
6.1 Writing the OTP Block ........................................................................................................................... 9
6.2 Reading the OTP Block ....................................................................................................................... 10
6.3 Read Command Structure ................................................................................................................... 11
7. QSPI Programming (Master Mode) ............................................................................................................ 11
8. MCU Programming (Slave Mode) ............................................................................................................... 13
Conclusion ........................................................................................................................................................... 14
9. Revision History .......................................................................................................................................... 15
1. Terms and Definitions
OTP One Time Programmable on chip NVM
QSPI Quad Serial Programming Interface
MCU Micro Controller Unit
FPGA Field-Programmable Gate Array
CPOL Clock Polarity
CPHA Clock Phase
2. References
[1] SLG47910, Datasheet, Renesas Electronics Corporation
[2] ForgeFPGA Designer Software , Software Download and User Guide, Renesas Electronics Corporation
[3] ForgeFPGA Dev. Board R1.1 User Guide
[4] ForgeFPGA Socket Adapter Quick Start Guide R1.0