Renesas ForgeFPGA, Руководство пользователя

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ForgeFPGA Configuration Guide
Rev.1.0
May 31, 2022 Page 10
Table 3: OTP Write Packet Format (Incoming)
Bits 0 1 2 3 4 5 6 7
Byte 1 W/Rn (1) SP/AP (0) R R R O1_A[15] O1_A[14] O1_A[13]
Byte 2 O1_A[12] O1_A[11] O1_A[10] O1_A[8] O1_A[7] O1_A[6] O1_A[5] O1_A[4]
Byte 3 O1_A[3] O1_A[2] O1_A[1] O1_A[0] O1_D[3] O1_D[2] O1_D[1] O1_D[0]
Byte 4 O2_A[15] O2_A[14] O2_A[13] O2_A[12] O2_A[11] O2_A[10] O2_A[8] O2_A[7]
Byte 5 O2_A[6] O2_A[5] O2_A[4] O2_A[3] O2_A[2] O2_A[1] O2_A[0] O2_D[3]
Byte 6 O2_D[2] O2_D[1] O2_D[0] O3_A[15] O3_A[14] O3_A[13] O3_A[12] O3_A[11]
Byte 7 O3_A[10] O3_A[8] O3_A[7] O3_A[6] O3_A[5] O3_A[4] O3_A[3] O3_A[2]
Byte 8 O3_A[1] O3_A[0] O3_D[3] O3_D[2] O3_D[1] O3_D[0] Last P
Address and Data
OTP1
OTP2
OTP3
Figure 11: OTP Write Waveforms
Table 4: Read/Write Option Bits
Byte 1 [0:1] of OTP Packet format Comments
2’b00: Read mode
Follows format in
Table 5
2’b01: Reserved
Not Used
2’b10: Write mode
Follows format in Table 3
2’b11: Return
Exit Read/Write OTP
6.2 Reading the OTP Block
Reading of the NVM via SPI is done by sending a three-byte command packet, which is met with a five-byte
response packet containing the requested NVM data. A diagram of the read command packet structure is given
in
Figure 12 .
Reading to the OTP has the following steps:
1. Waiting for POR and PLL lock time (1300 us), after that we are sending the Signature bytes through
SPI_MOSI (GPIO_5) by keeping SPI_SS (GPIO_4) low.
2. After Signature bytes matches, GPIO_9 (Config-Sig match) goes high and giving delay of 80 us and then
sending the OTP Read command packet on SPI_MOSI (GPIO_5) by keeping low SPI_SS (GPIO_4) and OTP
read data will come on SPI_MISO (GPIO_6).