CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
26
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Name R/W
Bit
After
Reset
Function
FE *
R
3
0
This bit is set to “1” when a framing error is detected in received data.
Reading this register clears this bit to “0”.
A framing error occurs when the first stop bit following the data bit or parity
bit of received data is checked and it is judged to be invalid (low level).
In FIFO mode, the framing error information is stored in the receive FIFO
with the receive data.
A framing error is detected when the data is read.
PE *
R
2
0
This bit is set to “1” when a parity error is detected in received data.
Reading this register clears this bit to “0”.
In FIFO mode, the parity error information is stored in the receive FIFO with
the received data.
A parity error is detected when the data is read.
OE *
R
1
0
This bit is set to “1” when a receive overrun error is detected. Reading this
register clears this bit to “0”.
A receive overrun occurs when the receive buffer register (RBR) or receive
FIFO is filled with received data, data is held in the receive shift register
(RSR), and the start bit of the following data is detected.
When a receive overrun error occurs, received data will no longer be stored
in the receive buffer register or receive FIFO.
Data held in the receive shift register is stored in the receive buffer when a
vacancy becomes available.
DR
R
0
0
This bit is set to "1" when at least 1 byte of received data is stored in the
receive buffer register (RBR) or receive FIFO.
This bit is cleared to "0" when all of the received data is read and the
receive buffer empties.
* Do not poll these bits to check the interrupt source. Instead, check the source after the interrupt is detected.
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