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APPENDIX

Appendix 2. Memory assignment in SFR area

7751 Group User’s Manual

20–8

Timer A0 interrupt control register

Timer A1 interrupt control register

UART1 receive interrupt control register

UART0 transmit interrupt control register

Access characteristics

State immediately after a reset

Watchdog timer frequency select register

60

16

61

16

62

16

63

16

64

16

65

16

66

16

67

16

68

16

69

16

70

16

71

16

72

16

73

16

74

16

75

16

76

16

77

16

78

16

79

16

7A

16

7B

16

7C

16

7D

16

7E

16

7F

16

6B

16

6C

16

6D

16

6E

16

6F

16

6A

16

RW

RW
RW

RW

b7

b0

(Note 1)

RW
RW

RW
RW

RW
RW
RW
RW
RW

RW

0

0

0

0

?

0

? (Note 2)

b7

b0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RW

RW

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RW

Address

A-D conversion interrupt control register

UART1 transmit interrupt control register

INT

2

interrupt control register

Register name

Watchdog timer register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B1 interrupt control register

Timer B2 interrupt control register

INT

0

interrupt control register

Timer B0 interrupt control register

INT

1

interrupt control register

Notes 1: By writing dummy data to address 60

16

, a value “FFF

16

” is set to the watchdog timer. The

dummy data is not retained anywhere.

2: The value “FFF

16

” is set tot the watchdog timer. (Refer to “Chapter 9. WATCHDOG TIMER.”)

UART0 receive interrupt control register

?
?
?

?

?
?
?

?
?
?
?

?
?
?

?

?
?

?

?
?

?
?
?
?
?

?
?
?

?

?

?

: It is possible to read the bit state at reading. The written value becomes valid data.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid data. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value is ignored.

RW
RO

WO

Access characteristics

: “0” immediately after a reset.
: “1” immediately after a reset.

:

Undefined immediately after

a reset.

0

1

?

: Always “0” at reading

0

0

: Always undefined at reading

: “0” immediately after a reset. Fix this bit to “0.”

?

State immediately after a reset

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458
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461
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Содержание 7700 FAMILY

Страница 1: ...ubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for...

Страница 2: ...MITSUBISHI 16 BIT SINGLE CHIP MICROCOMPUTER 7700 FAMILY 7751 SERIES 7751 Group User s Manual...

Страница 3: ...manual the users will be able to understand the functions so that they can utilize their capabilities fully For details concerning the software refer to the 7751 Series Software Manual For details con...

Страница 4: ...ister DPR 2 6 2 1 9 Processor status register PS 2 8 2 2 Bus interface unit 2 10 2 2 1 Overview 2 10 2 2 2 Functions of bus interface unit BIU 2 12 2 2 3 Operation of bus interface unit BIU 2 15 2 3 A...

Страница 5: ...rupt request bit 4 23 ___ 4 10 2 Switch of occurrence factor of INTi interrupt request 4 25 CHAPTER 5 TIMER A 5 1 Overview 5 2 5 2 Block description 5 3 5 2 1 Counter and reload register timer Ai regi...

Страница 6: ...ode register 7 4 7 2 2 UARTi transmit receive control register 0 7 6 7 2 3 UARTi transmit receive control register 1 7 7 7 2 4 UARTi transmit register and UARTi transmit buffer register 7 9 7 2 5 UART...

Страница 7: ...eat mode operation description 8 22 8 8 Single sweep mode 8 23 8 8 1 Settings for single sweep mode 8 23 8 8 2 Single sweep mode operation description 8 25 8 9 Repeat sweep mode 0 8 27 8 9 1 Settings...

Страница 8: ...function 12 14 12 3 1 Operation description 12 15 12 4 Hold function 12 18 12 4 1 Operation description 12 19 CHAPTER 13 RESET 13 1 Hardware reset 13 2 13 1 1 Pin state 13 3 13 1 2 State of CPU SFR ar...

Страница 9: ...ess in high speed running 15 33 15 12 Memory expansion mode and microprocessor mode When 4 access in high speed running 15 38 15 13 Memory expansion mode and microprocessor mode When 5 access in high...

Страница 10: ...to built in flash memory 19 5 19 1 3 Read only mode 19 7 19 1 4 Read write software command control mode 19 9 19 1 5 Electrical characteristics 19 18 19 1 6 Program erase algorithm flow chart 19 20 19...

Страница 11: ...Table of Contents viii 7751 Group User s Manual MEMORANDUM...

Страница 12: ...CHAPTER 1 DESCRIPTION 1 1 Performance overview 1 2 Pin configuration 1 3 Pin description 1 4 Block diagram...

Страница 13: ...concerning each microcomputer s development status of the 7751 Group inquire of CONTACT ADDRESSES FOR FURTHER INFORMATION described last 2 How the 7751 Group s type name see is described below M 3 77...

Страница 14: ...TA4 TB0 TB2 UART0 UART1 Functions 109 100 ns the minimum instruction at f XIN 40 MHz 40 MHz maximum at high speed running 49152 bytes 2048 bytes 8 bits 8 4 bits 1 16 bits 5 16 bits 3 UART or clock syn...

Страница 15: ...2 4 A 20 D 4 P7 4 AN 4 P7 5 AN 5 P7 6 AN 6 P7 7 AN 7 AD TRG V SS AV SS V REF AV CC V CC P8 0 CTS 0 RTS 0 P8 1 CLK 0 P8 2 R X D 0 P8 3 T X D 0 P84 CTS1 RTS1 P85 CLK1 P86 RXD1 P87 TXD1 P00 A0 P01 A1 P02...

Страница 16: ...d be left open _ This pin outputs E signal Data instruction code read or data write is performed when output from this pin is L level Memory expansion mode Microprocessor mode Input level to this pin...

Страница 17: ...ame function as P0 Memory expansion mode Microprocessor mode Data D0 to D7 input output and output of the high order 8 bits A16 A23 of the address are performed with the time sharing system Single chi...

Страница 18: ...1 output pin Microprocessor mode _____ ____ P40 functions as the HOLD input pin P41 as the RDY input pin P42 always functions as the clock 1 output pin P43 P47 function as I O ports with the same func...

Страница 19: ...t P0 Watchdog Timer CNVss BYTE External data bus width selection input Timer B1 16 Timer B2 16 P0 8 Timer B0 16 Timer A1 16 Timer A2 16 Timer A3 16 Timer A4 16 Timer A0 16 ROM 48 Kbytes RAM 2048 bytes...

Страница 20: ...CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 2 Bus interface unit 2 3 Access space 2 4 Memory assignment 2 5 Processor modes...

Страница 21: ...b8 b15 b7 b0 b8 b23 b16 b15 b7 b0 PCH PCL PG b0 b7 DT b0 b7 b8 b15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b10 0 0 0 0 0 C Z I D x m V N IPL Accumulator A A Accumulator B B Index register X X Index register Y Y St...

Страница 22: ...ster Flag x is a part of the processor status register which is described later When an 8 bit register is selected only the low order 8 bits of index register X are used and the contents of the high o...

Страница 23: ...nal registers in the reverse sequence PS PC PG by executing the RTI instruction The contents of S is returned to the state before accepting an interrupt request The same operation is performed during...

Страница 24: ...high order 8 bits bank of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored These 8 bits are...

Страница 25: ...ter indicate the direct page area which is allocated in bank 016 or in the space across banks 016 and 116 The following addressing modes use the direct page register The contents of the direct page re...

Страница 26: ...area when DPR FF1016 Note 2 Bank 016 Bank 116 016 FF16 12316 22216 FF1016 1000F16 016 FFFF16 1000016 Notes 1 The number of cycles required to generate an address is 1 cycle smaller when the low order...

Страница 27: ...s other than watchdog timer the BRK instruction and zero division Interrupts are disabled when this flag is 1 When an interrupt request is accepted this flag is automatically set to 1 to avoid multipl...

Страница 28: ...47483648 and 2147483647 in the RMPA instruction a Repeat MultiPly and Accumulate instruction When the BVC or BVS instruction is executed this flag s contents determine whether the program causes a bra...

Страница 29: ...rformed via the BIU Figure 2 2 1 shows the bus and bus interface unit BIU The BIU reads an instruction from the memory before the CPU executes it When the CPU reads data from the memory I O device the...

Страница 30: ...nal bus and external bus are independent of one another 2 Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES about control signals of the external bus Internal bus A 0 to A 23 External device Intern...

Страница 31: ...3 b15 b7 Table 2 2 1 Functions of each register Functions Indicates the storage address for the instruction which is next taken into the instruction queue buffer Temporarily stores the instruction whi...

Страница 32: ...truction queue buffer is initialized when a branch or jump instruction is executed and the BIU reads a new instruction from the destination address When instructions in the instruction queue buffer ar...

Страница 33: ...he bus cycle Table 2 2 2 shows the bus cycle at accessing the internal area Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES about the bus cycle at accessing the external devices Table 2 2 2 Bus c...

Страница 34: ...etches only 1 byte with the timing of waveform a The contents at the even address are not taken 2 When reading or writing data to and from the memory I O device When accessing a 16 bit data which begi...

Страница 35: ...unit BIU Address a Data Even address Data Odd address E Internal address bus A0 to A23 Internal data bus D0 to D7 Internal data bus D8 to D15 b Address Odd address Address Even address Data Even addre...

Страница 36: ...ingly it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory from I O devices Fig 2 3 1 M37751 s access space Indicates the memor...

Страница 37: ...as a result of subtraction the contents of the program bank register PG is decremented by 1 Normally accordingly the user can program without concern for bank boundaries SFR Special Function Register...

Страница 38: ...ach functional description in this manual For the state of the SFR area immediately after a reset refer to section 13 1 2 State of CPU SFR area and internal RAM area 2 Internal RAM area The M37751M6C...

Страница 39: ...FFE616 FFEA16 FFEE16 FFF016 FFF216 FFF416 FFF616 FFF816 FFFA16 FFFC16 FFFE16 Interrupt vector table 00007F16 00000016 00008016 00FFFF16 00FFD616 Internal RAM area Refer toFigure 2 4 2 L Notes 1 DBC i...

Страница 40: ...terrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control...

Страница 41: ...nt in each processor mode for M37751M6C XXXFP 00000016 00FFFF16 00008016 SFR area Internal ROM area Single chip mode Internal RAM area SFR area Memory expansion mode 01000016 FFFFFF16 SFR area Micropr...

Страница 42: ...nd the internal ROM area is handled as an external area In the microprocessor mode port P42 always functions as the clock 1 output pin In the memory expansion and microprocessor modes P0 to P3 P40 and...

Страница 43: ...7 TA3 IN P5 6 TA3 OUT P5 5 TA2 IN P5 4 TA2 OUT P5 3 TA1 IN P5 2 TA1 OUT P5 1 TA0 IN P5 0 TA0 OUT 25 27 26 28 34 29 30 31 32 33 35 36 37 38 39 40 1 4 3 2 5 A20 D4 A21 D5 A22 D6 A23 D7 R W BHE ALE HLDA...

Страница 44: ...NECTION WITH EXTERNAL DEVICES 2 P42 functions as a programmable I O port in the memory expansion mode and that functions as the clock 1 output pin by software selection Refer to Chapter 12 CONNECTION...

Страница 45: ...ocessor mode from the single chip mode to the memory expansion or microprocessor mode with the processor mode bits When the processor mode is switched during the program execution the contents of the...

Страница 46: ...his bit becomes 1 after a reset Fixed to 1 2 This bit is ignored in the microprocessor mode It may be either 0 or 1 Bit Bit name Functions At reset RW 0 1 2 3 4 5 6 7 Processor mode bits Software rese...

Страница 47: ...Bus cycle select bits 3 2 1 0 Bit name At reset 0 RW Functions In high speed running 0 0 5 access in high speed running 0 1 4 access in high speed running 1 0 3 access in high speed running 1 1 Not se...

Страница 48: ...CHAPTER 3 INPUT OUTPUT PINS 3 1 Programmable I O ports 3 2 I O pins of internal peripheral devices...

Страница 49: ...the I O pins of the internal peripheral devices For the functions refer to the section 3 2 I O pins of internal peripheral devices and relevant sections of each internal peripheral devices Fig 3 1 1...

Страница 50: ...t Port Pi3 direction bit Port Pi4 direction bit Port Pi6 direction bit 0 Input mode Functions as an input port 1 Output mode Functions as an output port Port Pi5 direction bit Port Pi direction regist...

Страница 51: ...port latch The data is output from the pin according to the contents of the port latch By reading the port register of a port set to output mode the contents of the port latch is read out instead of t...

Страница 52: ...the corres ponding bit Port Pi5 Port Pi register i 0 to 8 Addresses 216 316 616 716 A16 B16 E16 F16 1216 b1 b0 b2 b3 b4 b5 b6 b7 Port Pi1 Port Pi7 At reset RW Undefined Note Bits 7 to 4 of the port P...

Страница 53: ...Inside dotted line not included Ports P50 TA0OUT P52 TA1OUT P54 TA2OUT P56 TA3OUT P60 TA4OUT Inside dotted line included Data bus 1 Output Port latch Direction register P82 RxD0 P86 RxD1 Ports P40 P41...

Страница 54: ...er s Manual 3 7 INPUT OUTPUT PINS 3 1 Programmable I O ports Fig 3 1 5 Port peripheral circuits 2 E output pin Ports P80 CTS0 RTS0 P81 CLK0 P84 CTS1 RTS1 P85 CLK1 1 Output 0 Direction register Port la...

Страница 55: ...r to relevant sections of each internal peripheral device For the clock 1 output pin refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES Table 3 2 1 I O pins for internal peripheral devices I O pins...

Страница 56: ...nterrupt priority level detection circuit 4 6 Interrupt priority level detection time 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine 4 8 Return from interrupt rout...

Страница 57: ...quence When an interrupt request is accepted a branch is made to the start address of the interrupt routine set in the interrupt vector table addresses FFD616 to FFFF16 Set the start address of each i...

Страница 58: ...stored in order of registers and a return is made to the routine executed before the acceptance of interrupt request and processing is resumed from it When an interrupt request is accepted and the RTI...

Страница 59: ...terrupt sources and the interrupt vector addresses When programming set the start address of each interrupt routine at the vector addresses listed in this table 4 2 Interrupt sources Low order address...

Страница 60: ...ence factors Occurs when 0 is specified as the divisor for the DIV instruction Division instruction Refer to 7751 Series Software Manual Occurs when the BRK instruction is executed Refer to 7751 Serie...

Страница 61: ...instruction Watchdog timer interrupts An interrupt which is certain to be accepted when its request occurs These interrupts do not have their interrupt control registers and are independent of the in...

Страница 62: ...ssigned b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers Addresses 7D16 to 7F16 Bit 4 Interrupt request bit Note 2 1 0 Bit name At reset 0 RW Functions 0 0 0 Level 0 Interrupt disabled...

Страница 63: ...are used to determine the priority level of each interrupt Use the SEB or CLB instruction to set these bits When an interrupt request occurs its interrupt priority level is compared with the processor...

Страница 64: ...Enabled interrupt priority level Enable level 1 and above interrupts Enable level 2 and above interrupts Enable level 3 and above interrupts Enable level 4 and above interrupts Enable level 5 and abov...

Страница 65: ...Use the interrupt priority level select bits to set their priority levels Additionally the reset which is handled as one that has the highest priority of all interrupts and the watchdog timer interru...

Страница 66: ...etection circuit 4 5 Interrupt priority level detection circuit Fig 4 5 1 Interrupt priority level detection circuit A D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 T...

Страница 67: ...priority level is detectedd by the above comparison Then this highest interrupt priority level is compared with the processor interrupt priority level IPL When this interrupt priority level is higher...

Страница 68: ...upt priority level detection time Fig 4 6 1 Interrupt priority level detection time 2 Interrupt priority level detection time Op code fetch cycle Sampling pulse a 7 cycles b 4 cycles c 2 cycles Interr...

Страница 69: ...16 to FFFF16 The INTACK sequence is automatically performed in the following order The contents of the program bank register PG just before performing the INTACK sequence are stored to stack The conte...

Страница 70: ...d Undefined Next instruction Next instruction Vector address Low order Fig 4 7 2 INTACK sequence timing at minimum Duration for detecting interrupt priority level Interrupt request occurs Interrupt re...

Страница 71: ...n 4 9 Multiple interrupts When at reset or the watchdog timer or the software interrupt is accepted the value shown in Table 4 7 1 is set in the IPL Table 4 7 1 Change in IPL at interrupt request acce...

Страница 72: ...registers except the stack pointer S 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine Fig 4 7 3 Register storing operation Storing is completed with 3 times Stores 1...

Страница 73: ...ts disabled Interrupt request bit of the accepted interrupt 0 Processor interrupt priority level IPL interrupt priority level of the accepted interrupt Accordingly as long as the IPL remains unchanged...

Страница 74: ...pt 1 This request cannot be accepted because its priority level is lower than interrupt 1 s Request Time They are set automatically Set by software I Interrupt disable flag IPL processor interrupt pri...

Страница 75: ...the pin s state by reading bits 2 to 4 at address E16 port P6 register Note When selecting an input signal s falling or L level as the occurrence factor of an interrupt request make sure that the inpu...

Страница 76: ...1 Level 3 1 0 0 Level 4 1 0 1 Level 5 1 1 0 Level 6 1 1 1 Level 7 High level b2 b1 b0 0 No interrupt request 1 Interrupt request 0 Edge sense 1 Level sense Note The INT0 to INT2 interrupt request bit...

Страница 77: ...P6 direction register Address 1016 b1 b0 b2 b3 b4 b5 b6 b7 TA4IN pin TB2IN pin At reset RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 0 Input mode 1 Output mode When using pins as external interrupt inpu...

Страница 78: ...vel sense mode ___ The INTi interrupt request bit becomes ignored ___ In this case the interrupt request occurs continuously while the level of the INTi pin is valid level 1 ___ ___ When the INTi pin...

Страница 79: ...rrupts INTi interrupt First interrupt routine INTi pin level Valid Invalid Main routine Interrupt request is accepted Return to main routine Second interrupt routine Third interrupt routine Main routi...

Страница 80: ...ccurrence factor of INTi interrupt request Clear level sense edge sense select bit to 0 Select edge sense Clear interrupt request bit to 0 Set the interrupt priority level to level 0 Disable INTi inte...

Страница 81: ...to be inserted with program example of Figure 4 11 1 and the interrupt priority detection time select bits Fig 4 11 1 Program example to reserve time required for changing interrupt priority level Tab...

Страница 82: ...CHAPTER 5 TIMER A 5 1 Overview 5 2 Block description 5 3 Timer mode 5 4 Event counter mode 5 5 One shot pulse mode 5 6 Pulse width modulation PWM mode...

Страница 83: ...r counts an internally generated count source Following functions can be used in this mode Gate function Pulse output function Event counter mode The timer counts an external signal Following function...

Страница 84: ...4 f 16 f 32 f 64 f 128 f 512 f 1024 Count source select bits Timer mode One shot pulse mode PWM mode Polarity switching Timer mode Gate function Event counter mode Trigger Count start bit Down count U...

Страница 85: ...counter at the next reload time The value got when reading out the timer Ai register varies according to the operating mode Table 5 2 2 lists reading and writing from and to the timer Ai register Tab...

Страница 86: ...2 Structure of count start register Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1...

Страница 87: ...ing mode These bits are described in the paragraph of each operating mode Fig 5 2 3 Structure of timer Ai mode register Bit 7 5 4 3 1 Bit name At reset 0 0 0 0 0 0 0 0 RW Functions b7 b6 b5 b4 b3 b2 b...

Страница 88: ...s priority level is higher than the IPL However this applies when the interrupt disable flag I 0 To disable timer Ai interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is...

Страница 89: ...5 2 5 Relationship between port P5 and port P6 direction registers and Timer Ai s I O pins Bit Corresponding pin name Functions 0 1 2 3 4 5 6 7 TA0OUT pin TA1OUT pin TA1IN pin TA2OUT pin TA3OUT pin 0...

Страница 90: ...register Write to timer Ai register Specifications f2 f4 f16 f32 f64 f128 or f512 f1024 Down count When the counter underflows reload register s contents are reloaded and counting continues When count...

Страница 91: ...RW Gate function select bits Pulse output function select bit 1 Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 0 0 Timer...

Страница 92: ...ter Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4B16 4A16 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 Continue to Figure 5 3 3...

Страница 93: ...ing interrupt priority level b7 b0 Timer Ai interrupt control register i 0 to 4 Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disab...

Страница 94: ...ral devices select bit 0 Count source f4 f32 f128 f1024 f XIN 40 MHz b6 0 1 0 1 Count source select bits b7 0 0 1 1 Frequency 6 25 MHz 781 25 kHz 195 3125 kHz 24 4141 kHz Clock source for peripheral d...

Страница 95: ...quest is accepted or the interrupt request bit is cleared to 0 by software Figure 5 3 4 shows an example of operation in the timer mode Fig 5 3 4 Example of operation in timer mode without pulse outpu...

Страница 96: ...re 5 3 5 shows an example of operation selecting the gate function When selecting the gate function set the port P5 and port P6 direction registers bits which correspond to the TAiIN pin for the input...

Страница 97: ...Count valid level Timer Ai interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The counter counts when the count start bit 1 and the TAiIN pin s input signal...

Страница 98: ...s inverted each time the counter underflows When the count start bit address 4016 is 0 count stopped the TAiOUT pin outputs L level Figure 5 3 6 shows an example of operation selecting the pulse outpu...

Страница 99: ...e timer Ai register is read at the reload timing shown in Figure 5 3 7 the value FFFF16 is read out When reading the timer Ai register after setting a value to the register while counting is not in pr...

Страница 100: ...ignal input to the TAiIN pin The count source s valid edge can be selected between the falling and the rising edges by software Up count or down count can be switched by external signal or software Wh...

Страница 101: ...TAjOUT pin j 2 to 4 Up count or down count can be switched by external signal two phase pulse When the counter overflows or underflows reload register s contents are reloaded and counting is continue...

Страница 102: ...t bit Operating mode select bits 1 0 No pulse output TAiOUT pin functions as a programmable I O port 1 Pulse output TAiOUT pin functions as a pulse output pin 0 1 Event counter mode b1 b0 0 0 0 0 2 RW...

Страница 103: ...tents of up down register 1 Input signal to TAiOUT pin It may be either 0 or 1 Selection of event counter mode Setting divide ratio b7 b0 Can be set to 000016 to FFFF16 n b15 b8 b7 b0 Timer A0 registe...

Страница 104: ...n TA1OUT pin TA1IN pin TA2OUT pin TA2IN pin TA3OUT pin b7 b0 Port P6 direction register Address 1016 Clear the bit corresponding to the TAiIN pin to 0 When selecting the TAiOUT pin s input signal as u...

Страница 105: ...event counter mode When the count start bit is set to 1 the counter starts counting of the count source The counter counts the count source s valid edges When the counter underflows or overflows the...

Страница 106: ...pin s input signal is at H level When using the TAiOUT pin input signal to switch the up count down count set the port P5 and P6 direction registers bits which correspond to the TAiOUT pin for the in...

Страница 107: ...e pulse output function select bit bit 2 at addresses 5616 to 5A16 to 1 When this function is selected the TAiOUT pin is forcibly set for the pulse output pin regardless of the corresponding bits of t...

Страница 108: ...some bits of the port P5 and P6 direction registers correspond to pins used for two phase pulse input set these bits for the input mode Normal processing The timer up counts the rising edges to the T...

Страница 109: ...evel goes from H to L while the TA4OUT pin s input signal is H level Refer to Figure 5 4 8 Table 5 4 3 lists the input signals to the TA4OUT and TA4IN pins when the quadruple processing is selected Ta...

Страница 110: ...is not in progress and before the counter starts counting the set value is read out correctly Fig 5 4 9 Reading timer Ai register 2 The TAiOUT pin is used for all functions listed below Accordingly o...

Страница 111: ...f2 f4 f16 f32 f64 f128 or f512 f1024 Down count When the counter value becomes 000016 reload register s con tents are reloaded and counting stops If a trigger occurs during counting reload register s...

Страница 112: ...sed as follows n fi Undefined fi Frequency of count source f2 f4 f16 f32 f64 f128 or f512 f024 WO Trigger select bits Fix this bit to 1 in one shot pulse mode 1 Bit name Functions b7 b6 b5 b4 b3 b2 b1...

Страница 113: ...ecting one shot pulse mode and each function Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 1 Trigger select bits 0 0 0 1 1 0 Falling of TAiIN pin s input signal External trigger 1 1 Rising of...

Страница 114: ...t start bit Timer A4 one shot start bit Setting count start bit to 1 b7 b0 Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit...

Страница 115: ...r peripheral devices select bit 0 Count source f4 f32 f128 f1024 f XIN 40 MHz b6 0 1 0 1 Count source select bits b7 0 0 1 1 Frequency 6 25 MHz 781 25 kHz 195 3125 kHz 24 4141 kHz Clock source for per...

Страница 116: ...erated trigger and a new generated trigger 1 When selecting internal trigger A trigger is generated when writing 1 to the one shot start bit address 4216 Figure 5 5 4 shows the structure of the one sh...

Страница 117: ...to 1 This interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 5 5 5 shows an example of operation in the one...

Страница 118: ...by software Set to 1 by software Starts counting TAiIN pin input signal H One shot pulse output from TAiOUT pin H Trigger during counting 1 fi n Note The above applies when an external trigger rising...

Страница 119: ...is output Note The above applies when an external trigger falling of TAiIN pin s input signal is selected TAiIN pin s input signal H L Count source Trigger input Starts outputting of one shot pulse On...

Страница 120: ...tions f2 f4 f16 f32 f64 f128 or f512 f1024 Down count operating as an 8 bit or 16 bit pulse width modulator Reload register s contents are reloaded at rising of PWM pulse and counting continues A trig...

Страница 121: ...er A4 register Addresses 4F16 4E16 Functions Bit At reset RW 7 to 0 15 to 8 Undefined Undefined These bits can be set to 0016 to FF16 Assuming that the set value m PWM pulse s period output from the T...

Страница 122: ...16 4816 Timer A2 register Addresses 4B16 4A16 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 Note When operating as 16 bit pulse width modulator 216 1 fi n fi fi Frequency...

Страница 123: ...evel b7 b0 Timer Ai interrupt control register i 0 to 4 Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set thes...

Страница 124: ...evices select bit bit 2 at address 5F16 5 6 3 Trigger When a trigger is generated the TAiOUT pin starts outputting PWM pulses An internal or an external trigger can be selected as that trigger An inte...

Страница 125: ...r Figures 5 6 4 and 5 6 5 show operation examples of the 16 bit pulse width modulator 8 bit pulse width modulator When the 16 8 bit PWM mode select bit is set to 1 the counter is divided into 8 bit ha...

Страница 126: ...equest is accepted or cleared by software fi Frequency of count source f2 f4 f16 f32 f64 f128 or f512 f1024 When an arbitrary value is set to the timer Ai register after setting 000016 to it the timin...

Страница 127: ...er 8 bits n 0216 and low order 8 bits m 0216 and an external trigger falling of TAi IN pin input signal is selected H H H L L L 1 0 Timer Ai interrupt request bit Cleared to 0 when interrupt request i...

Страница 128: ...16 Counter s contents Hex 04 16 0A 16 Time When an arbitrary value is set to the timer Ai register after setting 00 16 to it the timing at which the PWM pulse level goes H depends on the timing at wh...

Страница 129: ...n was outputting L level the output level does not change and the timer Ai interrupt request does not occur 2 When setting the timer s operating mode in one of the followings the timer Ai interrupt re...

Страница 130: ...CHAPTER 6 TIMER B 6 1 Overview 6 2 Block description 6 3 Timer mode 6 4 Event counter mode 6 5 Pulse period pulse width measurement mode...

Страница 131: ...sures an external signal s pulse period or pulse width 6 2 Block description Figure 6 2 1 shows the block diagram of Timer B Explanation of registers relevant to Timer B is described below 6 1 Overvie...

Страница 132: ...erflows next time The counter value is read out by reading out the timer Bi register Note When reading and writing from to the timer Bi register perform them in a unit of 16 bits For more information...

Страница 133: ...Structure of count start register Bit Timer B2 count start bit Timer B1 count start bit Timer B0 count start bit Timer A4 count start bit Timer A3 count start bit Timer A2 count start bit Timer A1 co...

Страница 134: ...of timer Bi mode register Nothing is assigned These bits have different functions according to the operating mode 1 Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode...

Страница 135: ...ontrol register i 0 to 2 Addresses 7A16 to 7C16 Fig 6 2 4 Structure of timer Bi interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a timer Bi interrupt s p...

Страница 136: ...gister and Timer Bi s input pins 6 2 Block description Fig 6 2 5 Relationship between port P6 direction register and Timer Bi s input pins 0 1 2 3 4 5 6 7 TA4OUT pin INT0 pin INT1 pin INT2 pin TB1IN p...

Страница 137: ...rom timer Bi register Write to timer Bi register Specifications f2 f4 f16 f32 f64 f128 or f512 f1024 Down count When the counter underflows reload register s contents are reloaded and counting continu...

Страница 138: ...ing that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Undefined RW b7 b6 b5 b4 b3 b2 b1 b0 0 0 Bit This bit is ignored in...

Страница 139: ...B16 to 5D16 Setting count start bit to 1 b7 b0 Count start register Address 4016 Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit b7 b6 Setting interrupt priority level b7 b0...

Страница 140: ...ral devices select bit 0 Count source f4 f32 f128 f1024 f XIN 40 MHz b6 0 1 0 1 Count source select bits b7 0 0 1 1 Frequency 6 25 MHz 781 25 kHz 195 3125 kHz 24 4141 kHz Clock source for peripheral d...

Страница 141: ...til the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 6 3 3 shows an example of operation in the timer mode Stops counting Restarts counting FFFF16 n 00...

Страница 142: ...timer Bi register is read at the reload timing shown in Figure 6 3 4 the value FFFF16 is read out When reading the timer Bi register after setting a value to the register while counting is not in prog...

Страница 143: ...tions External signal input to the TBiIN pin The count source s valid edge can be selected from the falling edge the rising edge or both of the falling and rising edges by software Down count When the...

Страница 144: ...frequency by n 1 When reading the register indicates the counter value Undefined 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 1 0 Counts at both falling an...

Страница 145: ...gnal 0 1 Counts at rising of external signal 1 0 Counts at both of falling and rising of external signal 1 1 Not selected 0 1 Selecting event counter mode and count polarity Timer Bi mode register i 0...

Страница 146: ...r underflows in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 6 4 3 shows an example of operation i...

Страница 147: ...if the timer Bi register is read at the reload timing shown in Figure 6 4 4 the value FFFF16 is read out When reading the timer Bi register after setting a value to the register while counting is not...

Страница 148: ...request occurrence timing TBiIN pin function Read from timer Bi register Write to timer Bi register Specifications f2 f4 f16 f32 f64 f128 or f512 f1024 Up count Counter value is transferred to reload...

Страница 149: ...egister i 0 to 2 Addresses 5B16 to 5D16 1 0 Pulse period Pulse width measurement mode 7 0 0 f2 f4 0 1 f16 f32 1 0 f64 f128 1 1 f512 f1024 b7 b6 Count source select bits b1 b0 b3 b2 Nothing is assigned...

Страница 150: ...6 5 1 Setting for pulse period pulse width measurement mode Figure 6 5 2 shows an initial setting example for registers relevant to the pulse period pulse width measurement mode Note that when using i...

Страница 151: ...b0 Port P6 direction register Address 1016 Clear the corresponding bit to 0 TB0IN pin TB1IN pin TB2IN pin 0 0 Pulse period measurement Interval between falling edges of measured pulse 0 1 Pulse period...

Страница 152: ...25 MHz Clock source for peripheral devices select bit 0 Count source f4 f32 f128 f1024 f XIN 40 MHz b6 0 1 0 1 Count source select bits b7 0 0 1 1 Frequency 6 25 MHz 781 25 kHz 195 3125 kHz 24 4141 kH...

Страница 153: ...t valid edge is input after the timer starts counting 1 Pulse period pulse width measurement The measurement mode select bits bits 2 and 3 at addresses 5B16 to 5D16 specify whether the pulse period of...

Страница 154: ...unt timing of the count source The timer Bi overflow flag is a read only bit Use the timer Bi interrupt request bit to detect the overflow timing Do not use the timer Bi overflow flag to do that Figur...

Страница 155: ...s cleared to 000016 1 1 L 0 0 1 0 Count start bit Timer Bi interrupt request bit Timer Bi overflow flag Reload register counter transfer timing Counter is initialized by completion of measurement Coun...

Страница 156: ...d register when the first valid edge is input after the counter starts counting In this case the timer Bi interrupt request does not occur 4 The counter value at start of counting is undefined Accordi...

Страница 157: ...TIMER B 6 28 7751 Group User s Manual 6 5 Pulse period pulse width measurement mode MEMORANDUM...

Страница 158: ...7 1 Overview 7 2 Block description 7 3 Clock synchronous serial I O mode 7 4 Clock asynchronous serial I O UART mode CHAPTER 7 SERIAL I O...

Страница 159: ...ode Transmitter and receiver use the same clock as the transfer clock Transfer data has the length of 8 bits Clock asynchronous serial I O UART mode Transfer rate and transfer data format can arbitrar...

Страница 160: ...register Receive control circuit Transmit control circuit 1 n 1 1 16 1 16 1 2 BRGi Clock synchronous internal clock selected UART Clock synchronous UART Clock synchronous internal clock selected Clock...

Страница 161: ...s serial I O mode 0 1 0 Not selected 0 1 1 Not selected 1 0 0 UART mode Transfer data length 7 bits 1 0 1 UART mode Transfer data length 8 bits 1 1 0 UART mode Transfer data length 9 bits 1 1 1 Not se...

Страница 162: ...CLKi pin By setting this bit to 1 in order to select an external clock the clock input to the CLKi pin becomes the transfer clock UART mode By clearing this bit to 0 in order to select an internal clo...

Страница 163: ...bit is set to 1 It becomes H when reception starts and it becomes L when reception is completed 2 Transmit register empty flag bit 3 This flag is cleared to 0 when the UARTi transmit buffer register...

Страница 164: ...rformed clearing the receive enable bit to 0 reading the low order byte of the UARTi receive buffer register addresses 3616 3E16 out Bit 7 is cleared to 0 when all of bits 4 to 6 become 0 2 Bits 5 to...

Страница 165: ...transmit register This flag is cleared to 0 when data is set in the UARTi transmit buffer register 3 Receive enable bit bit 2 By setting this bit to 1 UARTi enters the reception enable state By cleari...

Страница 166: ...ection SP SP PAR 0 2SP 1SP UART 7 bit UART 8 bit UART 7 bit UART 9 bit UART Clock sync Clock sync Clock sync Data bus even Data bus odd TxDi UARTi transmit register Parity enabled Parity disabled D8 D...

Страница 167: ...with the transfer clock The UARTi transmit buffer register becomes empty when the data which is set in the UARTi transmit buffer register is transferred to the UARTi transmit register Accordingly the...

Страница 168: ...PAR 2SP 1SP UART 0 0 0 0 0 0 0 RxDi D8 D7 D6 D5 D4 D3 D2 D1 D0 SP Stop bit PAR Parity bit 8 bit UART 9 bit UART 7 bit UART 9 bit UART Clock sync Clock sync 7 bit UART 8 bit UART Data bus even Data bu...

Страница 169: ...uffer register is reversed and then the data of which bit position was reversed is read out as receive data Refer to section 7 3 2 Transfer data format Reception operation itself is the same whichever...

Страница 170: ...ngly writing to their addresses perform it while that is stopped Figure 7 2 10 shows the structure of the UARTi baud rate register BRGi Figure 7 2 11 shows the block diagram of transfer clock generati...

Страница 171: ...12 Structure of UARTi transmit interrupt control and UARTi receive interrupt control registers b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit interrupt control register Address 7116 UART0 receive interrupt co...

Страница 172: ...is higher than the IPL However this applies when the interrupt disable flag I 0 To disable the UARTi transmit receive interrupt set these bits to 0002 level 0 2 Interrupt request bit bit 3 The UARTi t...

Страница 173: ...t as I O pins of UARTi regardless of port P8 direction register s contents Figure 7 2 13 shows the relationship between the port P8 direction register and UARTi s I O pins Fig 7 2 13 Relationship betw...

Страница 174: ...e 7 3 2 Functions of I O pins in clock synchronous serial I O mode Functions Serial data output Serial data input Transfer clock output Transfer clock input ____ CTS input ____ RTS output Pin name TxD...

Страница 175: ...g relevant registers Select an internal clock bit 3 at addresses 3016 3816 0 Select the BRGi s count source bits 0 and 1 at addresses 3416 3C16 Set divide value 1 n 0016 to FF16 to the BRGi addresses...

Страница 176: ...ta in the UARTi receive buffer register is reversed and the resultant data is read out as the receive data Refer to the lower row in Table 7 3 3 Note that only the method of writing reading to and fro...

Страница 177: ...e When an internal clock is selected above precondition is ignored Transmission conditions Transmission is enabled transmit enable bit 1 Transmit data is present in the UARTi transmit buffer register...

Страница 178: ...ts 0 0 f2 f4 0 1 f16 f32 1 0 f64 f128 1 1 f512 f1024 b1 b0 1 0 0 0 UART0 transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 b0 Internal External clock sel...

Страница 179: ...ister Address 3A16 b7 b0 Writing of next transmit data Set transmit data here b0 UART0 transmit receive control register 1 Address 35 UART1 transmit receive control register 1 Address 3D b7 Transmit b...

Страница 180: ...transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 b7 b0 Checking completion of transmission Transmit register empty flag 0 During transmitting 1 T...

Страница 181: ...om the TxDi pin synchronously with the falling of the transfer clock This data is transmitted bit by bit sequentially beginning with the least significant bit When 1 byte data has been transmitted the...

Страница 182: ...mpty flag UARTi transmit interrupt request bit Data is set in UARTi transmit buffer register UARTi transmit register UARTi transmit buffer register Stopped because CTSi H Stopped because transmit enab...

Страница 183: ...e following precondition satisfied Precondition The CLKi pin s input is H level Note When an internal clock is selected above precondition is ignored Reception conditions Reception is enabled receive...

Страница 184: ...3016 UART1 transmit receive mode register Address 3816 b7 b0 Internal External clock select bit 0 Internal clock 1 External clock It may be either 0 or 1 Clock synchronous serial I O mode Continued to...

Страница 185: ...b7 b0 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 UART0 transmit buffer register Address 3216 UART1 trans...

Страница 186: ...e data Read out receive data b7 b0 Checking completion of reception 1 1 Note This figure shows the bits and registers required for processing Refer to Figure 7 3 11 about the change of flag state and...

Страница 187: ...ta is prepared in the UARTi receive register the contents of this register are transferred to the UARTi receive buffer register Simultaneously with step the receive complete flag is set to 1 and the U...

Страница 188: ...User s Manual 7 31 7 3 Clock synchronous serial I O mode Fig 7 3 10 Receive operation UARTi receive register D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D0 Receive data MSB b7 b0 LSB D2 D1 D0 Transfer clock UARTi r...

Страница 189: ...uffer empty flag Dummy data is set to UARTi transmit buffer register UARTi transmit register UARTi transmit buffer register Received data taken in UARTi receive register UARTi receive buffer register...

Страница 190: ...rror flag is set to 1 The overrun error flag is cleared to 0 by clearing the receive enable bit to 0 When an overrun error occurs during reception initialize the overrun error flag and the UARTi recei...

Страница 191: ...Set the transmit enable bit to 1 Write transmit data to the UARTi transmit buffer register ____ ____ Input L level to the CTSi pin when selecting the CTS function When receiving Set the receive enabl...

Страница 192: ...s in UART mode Method of selection Fixed Port P8 direction register 1 s corresponding bit 0 Internal External clock select bit 2 1 ____ ____ CTS RTS select bit 3 0 ____ ____ CTS RTS select bit 1 Pin n...

Страница 193: ...at addresses 3416 3C16 becomes the BRGi s count source When an external clock is selected the clock input to the CLKi pin becomes the BRGi s count source Tables 7 4 3 to 7 4 5 are list the setting exa...

Страница 194: ...select bit 1 Clock source for peripheral devices select bit 0 f XIN 24 576 MHz Clock source for peripheral devices select bit bit 2 at address 5F16 Table 7 4 5 Setting examples of transfer rate 3 Tran...

Страница 195: ...transmitter and receiver sides Figure 7 4 2 shows an example of transfer data format Table 7 4 6 lists each bit in transmit data Transfer data length of 7 bits 1ST 7DATA 1SP 1ST 7DATA 2SP 1ST 7DATA 1P...

Страница 196: ...order to improve data reliability The level of this signal changes according to selection of odd even parity in such a way that the sum of 1 s in this bit and character bits is always an odd or even...

Страница 197: ...smit data into that low order byte and bit 0 of that high order byte Transmission is started when all of the following conditions to are satisfied Transmit is enabled transmit enable bit 1 Transmit da...

Страница 198: ...UART1 transmit buffer register Addresses 3B16 3A16 b7 b0 Set transmit data here UART0 transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 b0 Internal Exte...

Страница 199: ...Addresses 3B16 3A16 b7 b0 Writing of next transmit data Set transmit data here b0 UART0 transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 Tran...

Страница 200: ...nsmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 b7 b0 Checking completion of transmission Transmit register empty flag 0 During transmitting 1 Tran...

Страница 201: ...d bit by bit sequentially in order of ST DATA LSB DATA MSB PAR SP according to the set transfer data format When the stop bit has been transmitted the transmission register empty flag is set to 1 indi...

Страница 202: ...upt request is accepted or cleared by software The above timing diagram applies to the following conditions Parity enabled 1 stop bit CTS function selected UARTi transmit register UARTi transmit buffe...

Страница 203: ...ant registers when receiving Reception is started when all of the following conditions and are satisfied Reception is enabled receive enable bit 1 The start bit is detected When using interrupts it is...

Страница 204: ...transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 b0 Receive enable bit 1 Reception enabled UART0 transmit receive mode register Address 3016...

Страница 205: ...UART1 transmit receive control register 1 Address 3D16 b7 b0 Receive complete flag 0 Reception not completed 1 Reception completed Checking completion of reception 1 UART0 transmit receive control reg...

Страница 206: ...nd are repeated at each rising of the transfer clock When one set of data has been prepared in other words the shift according to the selected data format has been completed the UARTi receive register...

Страница 207: ...he above timinig diagram applies to the following conditions Parity disabled 1 stop bit RTS function selected BRGi count source Receive enable bit Transfer clock Receive complete flag UARTi receive in...

Страница 208: ...hermore when any of the above errors occurs the error sum flag is set to 1 Accordingly the error sum flag informs the user whether any error has occurred or not The overrun error flag is cleared to 0...

Страница 209: ...has 1 in bit 7 and the address of the slave microcomputer with which communicates in bits 0 to 6 from the master microcomputer to all slave microcomputers All slave microcomputers receive data of step...

Страница 210: ...D conversion method succesive approximation conversion method 8 4 Absolute accuracy and differential non linearity error 8 5 Comparison voltage in 8 bit mode 8 6 One shot mode 8 7 Repeat mode 8 8 Sin...

Страница 211: ...w One shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin Repeat mode This mode is used to perform the operation repeatedly for a voltage i...

Страница 212: ...diagram of A D converter AVSS VREF Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG VIN 1 2 f2 f4 1 2 AD Decoder Register ladder network Successive approximation register A D register 2 A D register 3 A D r...

Страница 213: ...t Trigger select bit 4 A D operation mode select bits 0 2 1 0 Bit name At reset 0 Undefined RW Functions 0 0 0 AN0 selected 0 0 1 AN1 selected 0 1 0 AN2 selected 0 1 1 AN3 selected 1 0 0 AN4 selected...

Страница 214: ...ains set to 1 even after the operation is completed In the repeat mode repeat sweep mode 0 or repeat sweep mode 1 the A D converter continues operating until this bit is cleared to 0 by software 4 A D...

Страница 215: ...epeat sweep mode 1 Note 4 2 1 0 Bit name At reset 1 Undefined RW Functions Refer to A D conversion frequency AD select bit 0 bit 7 at address 1E16 See Table 8 2 1 0 Repeat sweep mode 0 1 Repeat sweep...

Страница 216: ...in AN2 pin AN3 pin AN4 pin AN5 pin AN6 pin AN7 pin b7 b0 A D register 0 Addresses 21 16 2016 A D register 1 Addresses 23 16 2216 A D register 2 Addresses 25 16 2416 A D register 3 Addresses 27 16 2616...

Страница 217: ...the IPL However this applies when the interrupt disable flag I 0 To disable the A D conversion interrupt set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when an A D...

Страница 218: ...p between the port P7 direction register and A D converter s input pins 8 2 Block description Fig 8 2 6 Relationship between port P7 direction register and A D converter s input pins Bit Corresponding...

Страница 219: ...successive approximation register After setting bit 8 of the successive approximation register to 1 the A D converter compares Vref with VIN Bit 8 changes according to the comparison result as follows...

Страница 220: ...2048 VREF V V V V V Successive approximation register A D converter halt 1st comparison 2nd comparison 3rd comparison 10th comparison Conversion complete 1st comparison result 2nd comparison result n9...

Страница 221: ...ersion method Fig 8 3 1 Ideal A D conversion characteristics in 10 bit mode 00016 00116 00216 00316 3FE16 3FF16 Analog input voltage VREF 1024 1 VREF 1024 2 VREF 1024 3 1021 VREF 1024 VREF 1024 1022 V...

Страница 222: ...mV 20 mV are selected as the analog input voltages The absolute accuracy 3 LSB indicates that when the analog input voltage is 25 mV the output code expected from an ideal A D conversion characteristi...

Страница 223: ...put code is output For example in the case of the 10 bit mode when VREF 5 12 V the 1 LSB width of an A D converter with ideal characteristics is 5 mV but if the differential non linearity error is 1 L...

Страница 224: ...reference voltage Vref VREF 28 n VREF 210 0 5 VREF 28 n VREF 28 0 5 VREF Reference voltage n Contents of successive approximation register Table 8 5 1 Comparison reference voltage of the M37751 s 8 bi...

Страница 225: ...nalog input pin is performed once and an A D conversion interrupt request occurs when the operation is completed 8 6 1 Settings for one shot mode Figure 8 6 1 shows an initial setting example of the o...

Страница 226: ...te the following registers when the A D conversion stops before trigger occurs Each bit of A D control register 0 except bit 6 Each bit of A D control register 1 0 AN1 AN2 AN3 AN5 AN6 AN7 AN4 AN0 b7 b...

Страница 227: ...rts operation when the input level to the ADTRG pin changes from H to L while the A D conversion start bit is 1 The A D conversion is completed after 49 cycles of AD in the 8 bit mode or 59 cycles of...

Страница 228: ...8 19 A D CONVERTER 8 6 One shot mode Trigger occur Convert input voltage from ANi pin A D converter halt A D converter interrupt request occur Conversion result A D register i Fig 8 6 2 Conversion op...

Страница 229: ...s performed repeatedly In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E16 remains set to 1 until it is cleared to 0 by software and...

Страница 230: ...of A D control register 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 b7 b0 A D control register 0 address 1E16 0 1 0 0 0 0 AN0 selected 0 0 1 AN1 selected 0 1 0 AN2 selected 0 1 1 AN3 selected 1 0 0 AN4 selecte...

Страница 231: ...anges from H to L while the A D conversion start bit is 1 The first A D conversion is completed after 49 cycles of AD in the 8 bit mode or 59 cycles of AD in the 10 bit mode Then the contents of the s...

Страница 232: ...ated in ascending sequence from the AN0 pin An A D conversion interrupt request occurs when the operation for all selected input pins are completed 8 8 1 Settings for single sweep mode Figure 8 8 1 sh...

Страница 233: ...tart bit to 1 b7 b0 A D control register 0 address 1E16 1 A D conversion start bit Selecting external trigger Selecting internal trigger Trigger occur Operation start Input falling edge to ADTRG pin 0...

Страница 234: ...input voltage from the AN0 pin when the input level to ______ the ADTRG pin changes from H to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the AN0 pin is comp...

Страница 235: ...in single sweep mode Trigger occur Convert input voltage from AN0 pin Conversion result A D register 0 A D register i A D register 1 Conversion result Conversion result A D converter halt A D convert...

Страница 236: ...d in ascending sequence from the AN0 pin In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E16 remains set to 1 until it is cleared to...

Страница 237: ...ns to 0 Set bit 7 to 0 when selecting external trigger AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A D control register 0 address 1E16 0 0 AN0 AN1 2 pins 0 1 AN0 to AN3 4 pins 1 0 AN0 to AN5 6 pins 1 1 AN0 to AN7...

Страница 238: ...2 When an external trigger is selected The A D converter starts conversion for the input voltage from the AN0 pin when the input level to ______ the ADTRG pin changes from H to L while the A D conver...

Страница 239: ...g 8 9 2 Conversion operation in repeat sweep mode 0 Trigger occur Convert input voltage from AN0 pin Conversion result A D register 0 A D register i A D register 1 Conversion result Conversion result...

Страница 240: ...ure 8 10 1 shows the analog input pin sweep operation As shown in Figure 8 10 1 the pin to be executed in the group of fewer frequencies changes sequently In this mode no A D conversion interrupt requ...

Страница 241: ...AN0 AN1 AN0 AN1 AN2 AN0 AN1 AN3 AN0 AN1 AN4 AN0 AN1 AN5 AN0 AN1 AN6 AN0 AN1 AN7 AN2 AN0 AN1 AN3 A D sweep pin select bit bits 1 0 at address 1F16 102 Group of more frequencies of use pins AN0 AN2 AN0...

Страница 242: ...register 0 except bit 6 Each bit of A D control register 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A D control register 0 address 1E16 0 0 AN0 1 pin 0 1 AN0 AN1 2 pins 1 0 AN0 to AN2 3 pins 1 1 AN0 to AN3 4...

Страница 243: ...A D conversion start bit is cleared to 0 by software 2 When an external trigger is selected The A D converter starts conversion for the input voltage from the AN0 pin when the input level to ______ t...

Страница 244: ...A D control register 1 ______ 2 When an external trigger is selected the AN7 ADTRG pin cannot be used as the analog input pin It is ______ because the AN7 ADTRG pin is not connected to the comparator...

Страница 245: ...7751 Group User s Manual 8 36 A D CONVERTER Precautions when using A D converter MEMORANDUM...

Страница 246: ...CHAPTER 9 WATCHDOG TIMER 9 1 Block description 9 2 Operation description 9 3 Precautions when using watchdog timer...

Страница 247: ...owing to terminating Stop mode Refer to Chapter 10 STOP MODE 9 1 Block description Figure 9 1 1 shows the block diagram of the watchdog timer Fig 9 1 1 Block diagram of watchdog timer 2Vcc detection c...

Страница 248: ...atchdog timer When dummy data is written to the watchdog timer register Refer to Figure 9 1 2 When the most significant bit of Watchdog timer becomes 0 When the STP instruction is executed Refer to Ch...

Страница 249: ...the structure of the watchdog timer frequency select register Fig 9 1 3 Structure of watchdog timer frequency select register 9 1 Block description 0 Wf512 Wf1024 1 Wf32 Wf64 At reset Undefined 0 RW F...

Страница 250: ...mes the watchdog timer interrupt request occurs Refer to Table 9 2 1 When the interrupt request occurs at above a value FFF16 is set to Watchdog timer The watchdog timer interrupt is a nonmaskable int...

Страница 251: ...timer interrupt routine 9 2 Operation description Fig 9 2 1 Example of program runaway detection by Watchdog timer RTI Main routine Watchdog timer interrupt routine Watchdog timer register Address 60...

Страница 252: ...atchdog timer starts counting of the count source Wf32 Wf64 from FFF16 Supply of the CPU and BIU starts when the Watchdog timer s most significant bit becomes 0 At this time the watchdog timer interru...

Страница 253: ...is simultaneously performed Accordingly when the user does not want to change a value of the watchdog timer frequency select bit bit 0 at address 6116 write the previous value to the bit simultaneousl...

Страница 254: ...CHAPTER 10 STOP MODE 10 1 Clock generating circuit 10 2 Operation description 10 3 Precautions for Stop mode...

Страница 255: ...ircuit Q XIN XOUT R S Q R S Q R S 1 BIU CPU 1 8 f2 f4 1 4 1 8 f16 f32 f64 f128 f512 f1024 Wf512 Wf1024 Interrupt request STP instruction Reset WIT instruction Ready request Request of CPU wait from BI...

Страница 256: ...ter state and operation in and after Stop mode Table 10 2 1 Microcomputer state and operation in and after Stop mode State and Operation Item Stopped Operating enabled only in event counter mode Opera...

Страница 257: ...description Enabled in event counter mode Enabled when selecting external clock Notes 1 Since the oscillator has stopped oscillating each function does not work unless they are operated under the abov...

Страница 258: ...formed to terminate Stop mode or a system reset was performed use software after a reset Refer to Chapter 13 RESET for details about a reset 10 2 Operation description CPU 1 0 7FF16 FFF16 Stop mode f...

Страница 259: ...tion is always enabled in the built in PROM version and the flash memory version 2 When executing the STP instruction after writing to the internal area or an external area the three NOP instructions...

Страница 260: ...CHAPTER 11 WAIT MODE 11 1 Clock generating circuit 11 2 Operation description 11 3 Precautions for Wait mode...

Страница 261: ...ircuit Q XIN XOUT R S Q R S Q R S 1 BIU CPU 1 8 f2 f4 1 4 1 8 f16 f32 f64 f128 f512 f1024 Wf512 Wf1024 Interrupt request STP instruction Reset WIT instruction Ready request Request of CPU wait from BI...

Страница 262: ...n in and after Wait mode Table 11 2 1 Microcomputer state and operation in and after Wait mode State and Operation Item Operating Stopped Operating Operating Retains the same state in which the WIT in...

Страница 263: ...mode is terminated by the first interrupt request 11 2 2 Termination by hardware reset The CPU and the SFR area are initialized in the same way as a system reset However the internal RAM area retains...

Страница 264: ...g to the internal area or an external area the three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed 11 3 Precautions for Wait mode STA NOP NOP...

Страница 265: ...7751 Group User s Manual WAIT MODE 11 6 11 3 Precautions for Wait mode MEMORANDUM...

Страница 266: ...CHAPTER 12 CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices 12 2 Bus cycle 12 3 Ready function 12 4 Hold function...

Страница 267: ...e refer to sections 12 2 Bus cycle 12 3 Ready function and 12 4 Hold function as well as this section 12 1 1 Descriptions of signals When an external device is connected operate the microcomputer in t...

Страница 268: ...4 3 P4 2 1 External data bus width 16 bits BYTE L As 1 in microprocessor mode External address bus external data bus bus control signal RDY A20 D4 A21 D5 A22 D6 A23 D7 R W BHE ALE HLDA Vss E XOUT XIN...

Страница 269: ...put output timing of each signal 12 1 2 Operation of bus interface unit BIU 12 2 Bus cycle 12 3 Ready function 12 4 Hold function Chapter 15 ELECTRICAL CHARACTERISTICS HLDA BHE ALE R W HLDA D P RDY 1...

Страница 270: ...external data bus width is 16 bits the A8 D8 to A15 D15 and A16 D0 to A23 D7 pins perform address output and data input output with time sharing When the BYTE pin level is H i e external data bus widt...

Страница 271: ...gh enable signal BHE This signal indicates the access to an odd address This signal becomes L level when accessing an only odd address or when simultaneously accessing odd and even addresses This sign...

Страница 272: ...ection time select bits Clock 1 output select bit Note 2 0 0 0 0 0 0 Single chip mode 0 1 Memory expansion mode 1 0 Microprocessor mode 1 1 Not selected The microcomputer is reset by writing 1 to this...

Страница 273: ...bus width the BIU fetches only 1 byte with the waveform d When in the 8 bit external data bus width the BIU fetches only 1 byte with the first half of waveform f When a branch to an odd address is cau...

Страница 274: ...A8 D8 to A15 D15 BHE E A0 ALE A16 D0 to A23 D7 a Access from even address 16 bit data access External data bus width 16 bits BYTE L Address Data odd Data even Address Address b Access from odd addres...

Страница 275: ...access e Access from even address Address Address Data Data 8 bit data access 16 bit data access Address Address Address Address Data Address Data Address Address Address Address Address 8 bit data a...

Страница 276: ...2 2 1 shows the structure of the processor mode register 1 address 5F16 Table 12 2 2 lists each bus cycle The selection of bus cycle is valid only for external areas For the internal area the access i...

Страница 277: ...Not selected Note Fix this bit to 0 when f XIN 25 MHz Fix these bits to 0 4 7 6 RW RW RW RW 0 0 0 Clock source for peripheral devices select bit Note 0 divided by 2 1 CPU running speed select bit Note...

Страница 278: ...SFR ALE Reading Writing Note Signals when accessing an internal area means signals which are output from pins externally when accessing an internal area in the memory expansion mode A Address W Data t...

Страница 279: ...internal peripheral devices can operate Ready function is valid for the internal and external areas Table 12 3 1 Microcomputer s state in Ready state State Operating Stopped at L Retains the state whe...

Страница 280: ...microcomputer enters Ready state This is called acceptance of Ready request ____ In Ready state the input level of the RDY pin is judged at every falling of the clock 1 Then when H level is detected...

Страница 281: ...with the clock 1 indicated by and clocks BIU and CPU stop at L level Ready state is terminated Input level to the RDY pin is not judged during the term unusing the bus or before the condition above No...

Страница 282: ...t L level Ready state is terminated Input level to the RDY pin is not judged during the term unusing the bus or before the condition above Notes 1 The timing of ALE signal differs depending on low spe...

Страница 283: ...lation of the oscillator does not stop Accordingly the internal peripheral devices can operate However Watchdog timer stops operating Table 12 4 1 Microcomputer s state in Hold state Item Oscillation...

Страница 284: ...changes H to L When 1 cycle of BIU has passed after the level of HLDA pin becomes L pins R W ___ BHE and the external bus become floating state _____ In Hold state the input level of the HOLD pin is j...

Страница 285: ...Internal area access External area access Note Note Reading Reading Writing ALE Reading Writing E A A W BIU Clock 1 2 access in low speed running Judgment timing of input level to HOLD pin 2 access in...

Страница 286: ...nt timing of input level to HOLD pin External address bus External data bus Floating Floating Floating Address A Address B 1 1 Hold state Term using bus Term unusing bus This is the term in which the...

Страница 287: ...sing External address bus External data bus ALE Clock 1 1 1 Address B Address A Data Floating Floating Address A Floating Hold state Term using bus Term using bus When accepting a Hold request not a n...

Страница 288: ...External data bus Address A 1 1 1 Not accepted Address A Data Data Floating Floating Floating Hold state Term using bus Term using bus When accepting a Hold request not a new address but an address ou...

Страница 289: ...CONNECTION WITH EXTERNAL DEVICES 12 4 Hold function 7751 Group User s Manual 12 24 MEMORANDUM...

Страница 290: ...CHAPTER 13 RESET 13 1 Hardware reset 13 2 Software reset...

Страница 291: ...alizes pins within a term of several ten ns Refer to Table 13 1 1 ______ While the RESET pin is L level and within the term of 4 to 5 cycles of the internal clock after the ______ RESET pin goes from...

Страница 292: ...pins of P51 and P52 Outputs H level Floating Pin Port name P0 to P8 _ E P0 to P8 _ E P0 P1 P3 to P8 P2 CNVSS pin level Vss or Vcc Vss Vcc Note 1 _ E P0 to P8 _ E P0 P1 P3 to P8 P2 Flash memory versio...

Страница 293: ...a reset Undefined immediately after a reset Data bank register DT 0016 b7 b0 Program bank register PG 0016 b7 b0 Program counter PC Contents at address FFFE16 Contents at address FFFF16 b7 b0 b15 b8...

Страница 294: ...r Port P7 direction register Port P8 register A D control register 0 Port P0 register Port P1 register Port P2 register Port P3 register Port P0 direction register Port P1 direction register Port P2 d...

Страница 295: ...0 UART1 transmit receive control register 1 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 2816 2916 2B16 2C16 2D16 2E16 2F16 2A16 2016 2116 2216 2316 2416 2516 2616 2716...

Страница 296: ...te 2 Note 2 b7 b0 RW Note 2 Note 2 RW RW RW RW RW RW WO State immediately after a reset 0016 0016 0016 0016 0016 b7 b0 0016 WO RW Note 1 Note 1 Note 1 Note 1 Note 1 RW Timer A0 mode register Timer A4...

Страница 297: ...ntrol register Access characteristics RW b7 b0 RW State immediately after a reset 0 Note 2 b7 b0 UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control...

Страница 298: ...Vss 2 In microprocessor mode CNVss Vcc CPU AH CPU AMAL CPU DATA CPU E 000016 0016 FFFE16 ADM ADL ADM ADL 0016 0016 ALE A19 A16 A15 A0 D15 D0 E ALE 000016 016 FFFE16 ADM ADL ADM ADL 016 016 Next op cod...

Страница 299: ...ating including a power on reset and In Stop mode supply L level until the oscillation is stabilized The time to stabilize oscillation varies according to the oscillator For details contact the oscill...

Страница 300: ...13 11 13 1 Hardware reset 1 IN OUT GND Delay capacity RESET Vcc Vss 47 SW Cd GND 3 2 5 5V M51957AL M37751 27k 10k 4 The delay time is about 11 ms when Cd 0 033 F td 0 34 Cd s Cd pF Vcc Fig 13 1 9 Exa...

Страница 301: ...dresses which are FFFE16 and FFFF16 i Bit Bit name Functions At reset RW 0 1 2 3 4 5 6 7 Processor mode bits Software reset bit Interrupt priority detection time select bits Clock 1 output select bit...

Страница 302: ...CHAPTER 14 CLOCK GENERATING CIRCUIT 14 1 Oscillation circuit example 14 2 Clock...

Страница 303: ...or oscillator Figure 14 1 1 shows an example when connecting a ceramic resonator quartz crystal oscillator between pins XIN and XOUT The circuit constants such as Rf Rd CIN and COUT shown in Figure 14...

Страница 304: ...Ready request CPU BIU Hold request 1 8 1 16 Wf32 Wf64 1 Operation clock for internal peripheral devices Request of CPU wait from BIU Clock source for peripheral devices select bit CPU Central Process...

Страница 305: ...s clock source is or divided by 2 Refer to 14 2 2 Operation clock for internal peripheral devices Table 14 2 1 Operation clock for internal peripheral devices Operation clock Clock source for peripher...

Страница 306: ...ister 1 Address 5F16 Bit 5 Bus cycle select bits 3 2 1 0 Bit name At reset 0 RW Functions In high speed running 0 0 5 access in high speed running 0 1 4 access in high speed running 1 0 3 access in hi...

Страница 307: ...CLOCK GENERATING CIRCUIT 7751 Group User s Manual 14 6 14 2 Clock MEMORANDUM...

Страница 308: ...microprocessor mode When 3 access in low speed running 15 10 Memory expansion mode and microprocessor mode When 4 access in low speed running 15 11 Memory expansion mode and microprocessor mode When 3...

Страница 309: ...arameter Power source voltage Analog power source voltage Input voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ta 25 C Ratings 0 3 to 7 0 3...

Страница 310: ...5 VCC 0 0 0 P00 P07 P30 P33 P40 P47 P50 P57 P60 P67 P70 P77 ______ P80 P87 XIN RESET CNVSS BYTE P10 P17 P20 P27 in single chip mode P10 P17 P20 P27 in memory expansion mode and microprocessor mode P0...

Страница 311: ...67 P70 P77 P80 P87 P00 P07 P10 P17 P20 P27 P30 P31 P33 P32 E RESET XIN P00 P07 P10 P17 P20 P27 P30 P33 P40 P47 P50 P57 P60 P67 P70 P77 P80 P87 XIN RESET CNVSS BYTE P00 P07 P10 P17 P20 P27 P30 P33 P40...

Страница 312: ...wise noted Unit RLADDER tCONV VREF VIA Parameter Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Test conditions VREF VCC VREF VCC VREF VCC f XIN...

Страница 313: ...16 109 f XIN 16 109 f XIN 8 109 f XIN f XIN 40 MHz f XIN 25 MHz when divided by 2 selected as clock source for peripheral devices f XIN 25 MHz when selected as clock source for peripheral devices 200...

Страница 314: ...el pulse width TAiIN input low level pulse width Limits Min 2000 1000 1000 400 400 Max ns ns ns ns ns Unit Parameter Symbol Timer A input Up down input in event counter mode tc UP tw UPH tw UPL tsu UP...

Страница 315: ...ected TAiOUT input up down input th TIN UP tsu UP TIN Count input in event counter mode Gating input in timer mode External trigger input in one shot pulse mode External trigger input in pulse width m...

Страница 316: ...vices 400 640 320 ns 16 109 f XIN 16 109 f XIN 8 109 f XIN f XIN 40 MHz f XIN 25 MHz when divided by 2 selected as clock source for peripheral devices f XIN 25 MHz when selected as clock source for pe...

Страница 317: ...ded by 2 selected as clock source for peripheral devices f XIN 25 MHz when selected as clock source for peripheral devices 200 320 160 ns 8 109 f XIN 8 109 f XIN 4 109 f XIN Notes 1 TBiIN input cycle...

Страница 318: ...LKi input high level pulse width CLKi input low level pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time tc CK tw CKH tw CKL td C Q th C Q tsu D C th C D Symb...

Страница 319: ...onditions VCC 5 V 10 Input timing voltage VIL 1 0 V VIH 4 0 V Output timing voltage VOL 0 8 V VOH 2 0 V TBiIN input tc TB tw TBH tw TBL tc AD tw ADL ADTRG input tw INL tw INH INTi input tc CK tw CKH t...

Страница 320: ...ics VCC 5 V 10 VSS 0 V Ta 20 to 85 C f XIN 40 MHz unless otherwise noted Limits Min 40 40 0 0 Max ns ns ns ns Unit Parameter ____ RDY input setup time _____ HOLD input setup time ____ RDY input hold t...

Страница 321: ...iming voltage VOL 0 8 V VOH 2 0 V 1 When 2 access in low speed running 1 When 3 access and 4 access in low speed running and 4 access in high speed running RDY input Ready function E output E output R...

Страница 322: ...voltage VIL 1 0 V VIH 4 0 V Output timing voltage VOL 0 8 V VOH 2 0 V When 3 access in high speed running RDY input E output 1 tsu RDY 1 th 1 RDY 1 When 5 access in high speed running E output RDY inp...

Страница 323: ...P6 input hold time Port P7 input hold time Port P8 input hold time Symbol Parameter Unit Limits Max Min 60 60 60 60 60 60 60 60 60 ns ns ns ns ns ns ns ns ns Limits Unit Parameter Symbol Note For test...

Страница 324: ...E th E P5D td E P6Q tsu P6D E th E P6D td E P7Q tsu P7D E th E P7D td E P8Q tsu P8D E th E P8D tW L Single chip mode Test conditions VCC 5 V 10 Input timing voltage Output timing voltage VIL 1 0 V VIH...

Страница 325: ...input cycle time External clock input high level pulse width External clock input low level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup...

Страница 326: ...time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE ou...

Страница 327: ...Port P0 address hold time Port P1 address hold time BYTE L Port P1 data hold time BYTE L Port P1 floating release delay time BYTE L Port P1 address hold time BYTE H Port P2 address hold time Port P2 d...

Страница 328: ...E td E ALE tw ALE td R W E th E R W td E PiQ Memory expansion mode and Microprocessor mode When 2 access in low speed running Write XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test cond...

Страница 329: ...low speed running Read th E P1D th ALE P1A Data td P2A E tpzx E P2Z th E P2D Address th E PiD tsu PiD E XIN 1 Address output A0 A7 BHE output Test conditions 1 E P0 P3 VCC 5 V 10 Output timing voltage...

Страница 330: ...input cycle time External clock input high level pulse width External clock input low level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup...

Страница 331: ...ime Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE out...

Страница 332: ...Port P0 address hold time Port P1 address hold time BYTE L Port P1 data hold time BYTE L Port P1 floating release delay time BYTE L Port P1 address hold time BYTE H Port P2 address hold time Port P2 d...

Страница 333: ...LE tw ALE td R W E th E R W td E PiQ Memory expansion mode and Microprocessor mode When 3 access in low speed running Write Address XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test cond...

Страница 334: ...low speed running Read th E P1D th ALE P1A Data td P2A E tpzx E P2Z tpxz E P2Z th E P2D th ALE P2A Address th E PiD tsu PiD E XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test conditions...

Страница 335: ...k input cycle time External clock input high level pulse width External clock input low level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setup...

Страница 336: ...y time BYTE L Port P1 floating start delay time BYTE L Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 addr...

Страница 337: ...s hold time Port P1 address hold time BYTE L Port P1 data hold time BYTE L Port P1 floating release delay time BYTE L Port P1 address hold time BYTE H Port P2 address hold time Port P2 data hold time...

Страница 338: ...LE td R W E th E R W td E PiQ Memory expansion mode and Microprocessor mode When 4 access in low speed running Write Address Address XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test con...

Страница 339: ...ess in low speed running Read Data tsu P1D E th E P1D td P2A E tpzx E P2Z tpxz E P2Z Address th ALE P2A Data th E P2D th E PiD XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test condition...

Страница 340: ...ck input cycle time External clock input high level pulse width External clock input low level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setu...

Страница 341: ...elay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time A...

Страница 342: ...ss hold time Port P1 address hold time BYTE L Port P1 data hold time BYTE L Port P1 floating release delay time BYTE L Port P1 address hold time BYTE H Port P2 address hold time Port P2 data hold time...

Страница 343: ...d P1A E Address th E P1Q td P1A E Data td E P1Q Data th E P2Q td P2A E td E P2Q td E ALE td P1A ALE th ALE P1A td P2A ALE th ALE P2A XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test con...

Страница 344: ...running Read Data th E P1D th E PiD td P2A E tpzx E P2Z Data tsu P2D E th E P2D tsu P1D E Address XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test conditions P4 P8 VCC 5 V 10 Input tim...

Страница 345: ...ck input cycle time External clock input high level pulse width External clock input low level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setu...

Страница 346: ...P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time ALE output delay time ALE output delay...

Страница 347: ...ss hold time Port P1 address hold time BYTE L Port P1 data hold time BYTE L Port P1 floating release delay time BYTE L Port P1 address hold time BYTE H Port P2 address hold time Port P2 data hold time...

Страница 348: ...th E R W td E PiQ Memory expansion mode and Microprocessor mode When 4 access in high speed running Write td E ALE td P2A E Address XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test con...

Страница 349: ...ess in high speed running Read Data tsu P1D E th E P1D th E PiD td P2A E tpzx E P2Z Data tsu P2D E th E P2D XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test conditions P4 P8 VCC 5 V 10...

Страница 350: ...ck input cycle time External clock input high level pulse width External clock input low level pulse width External clock rise time External clock fall time Port P1 input setup time Port P2 input setu...

Страница 351: ...t delay time Port P8 data output delay time high level pulse width low level pulse width 1 output delay time _ E low level pulse width Port P0 address output delay time Port P1 data output delay time...

Страница 352: ...ss hold time Port P1 address hold time BYTE L Port P1 data hold time BYTE L Port P1 floating release delay time BYTE L Port P1 address hold time BYTE H Port P2 address hold time Port P2 data hold time...

Страница 353: ...th E P2Q td E P2Q th ALE P1A th ALE P2A td P1A ALE td P2A ALE td R W E td BHE E td E ALE tw ALE td ALE E th E BHE th E R W td E PiQ XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Test cond...

Страница 354: ...ss Address tpxz E P1Z th ALE P1A td P1A ALE td R W E td BHE E td E ALE tw ALE td ALE E th E BHE th E PiD Data th E P1D tsu P1D E th E R W XIN 1 Address output A0 A7 BHE output Port Pi output i 4 8 Tes...

Страница 355: ...time Port P2 address output delay time ALE output delay time ALE output delay time ALE pulse width ____ BHE output delay time __ R W output delay time Port P0 address hold time Port P1 address hold t...

Страница 356: ...P2A td P2A ALE th E BHE td BHE E td ALE E td E ALE Memory expansion mode and Microprocessor mode When 2 access in high speed running Internal RAM access Write The undefined value is output Address XIN...

Страница 357: ...tc td E 1 td P1A E td P1A E th E P1A Address td P1A ALE td BHE E th E BHE td R W E tw ALE th E R W tpzx E P1Z Address tpzx E P2Z The contents of external data bus cannot be read into the internal XIN...

Страница 358: ...7751 Group User s Manual 15 51 _ 15 15 Testing circuit for ports P0 to P8 1 and E _ 15 15 Testing circuit for ports P0 to P8 1 and E _ Fig 15 15 1 Testing circuit for ports P0 to P8 1 and E P0 P1 P2 P...

Страница 359: ...ELECTRICAL CHARACTERISTICS 7751 Group User s Manual 15 52 MEMORANDUM 15 15 Testing circuit for ports P0 to P8 1 and E...

Страница 360: ...CHAPTER 16 STANDARD CHARACTERISTICS 16 1 Standard characteristics...

Страница 361: ...XXFP s characteristics and are not guaranteed For rated values refer to Chapter 15 ELECTRICAL CHARACTERISTICS 16 1 1 Programmable I O port CMOS output standard characteristics 1 P channel IOH VOH char...

Страница 362: ...eristics on operating and at reset Measuring conditions VCC 5 0 V Ta 25 C f XIN square waveform 0 10 20 30 40 10 20 f XIN MHz I CC mA On operating in single chip mode At reset 2 Icc f XIN standard cha...

Страница 363: ...e when the output code changes For example the change in output code from 15 to 16 should occurs at 77 5 mV but the measured value is 1 2 mV Accordingly the measured point of change is 77 5 1 2 76 3 m...

Страница 364: ...STANDARD CHARACTERISTICS 16 1 Standard characteristics 7751 Group User s Manual 16 5 Measuring conditions Vcc 5 12 V VREF 5 12 V f XIN 40 MHz Ta 25 C...

Страница 365: ...STANDARD CHARACTERISTICS 16 1 Standard characteristics 7751 Group User s Manual 16 6 MEMORANDUM...

Страница 366: ...CHAPTER 17 APPLICATIONS 17 1 Memory expansion...

Страница 367: ...nnecting the memory of which external data bus width is 8 bits 2 Medium model A This is an expansion model of which external data bus width is 8 bits and accessible area is expanded up to 16 Mbytes In...

Страница 368: ...DEVICES for details about the functions and operation of used pins when expanding a memory Refer to Chapter 15 ELECTRICAL CHARACTERISTICS for timing requirements 2 Because the address bus width is us...

Страница 369: ...te tsu D tsu D tw EL td E P2Q P1Q td E P2Q P1Q td E P2Q or td E P1Q Table 17 1 2 lists the data or the calculation formulas for each parameter Figure 17 1 1 shows the bus timing diagram Figures 17 1 2...

Страница 370: ...ernal memory s External data bus width 8 bits BYTE H External data bus width 16 bits BYTE L External memory output data Data Address low order Address middle order Address middle order Address high or...

Страница 371: ...5 389 351 319 292 268 247 229 212 198 185 173 310 268 235 207 185 Operation clock frequency f XIN MHz ns Port Pi data setup time with address stabilized t su P0A P1A P2A P1D P2D 4 access in low speed...

Страница 372: ...72 67 63 60 56 53 50 MHz ns Operation clock frequency f XIN Port Pi data setup time with address stabilized t su P0A P1A P2A P1D P2D 5 access in high speed running 4 access in high speed running 3 ac...

Страница 373: ...to 3 Precautions on memory expansion Fig 17 1 6 Timing at which data is read from external memory External memory data output 1 This applies when the external data bus has a width of 16 bits BYTE L Ex...

Страница 374: ...2Z unit ns Parameter Bus cycle Low speed running 2 access Low speed running 3 access Low speed running 4 access High speed running 3 access High speed running 4 access High speed running 5 access tpxz...

Страница 375: ...iming at which data is written to external memory Table 17 1 4 Data of td E P1Q P2Q and calculation formulas of th E P1Q P2Q unit ns Parameter Bus cycle Low speed running 2 access Low speed running 3...

Страница 376: ...AD If the M37751 s tsu P1D P2D E cannot be satisfied because the external memory requires a long access time ta AD examine the method described below Lower f XIN Select a long bus cycle by software Re...

Страница 377: ...n f XIN 25 MHz 2 access in low speed running Ready function is available only for areas accessed by CS2 Sum of propagation delay time for AC32 AC74 and AC04 max 26 ns 1 2 3 1 1 2 Use the elements of w...

Страница 378: ...it CS2 1 2 3 1 to 3 f XIN 25 MHz 40 ns 2 10 f XIN tsu RDY 1 9 Ready function is available only for areas accessed by CS2 Use the elements of which sum of propagation delay time is within Circuit condi...

Страница 379: ...is tc 35 25 ns Accordingly when f XIN 28 MHz this circuit example satisfies tsu RDY 1 40 ns tsu RDY 1 tsu RDY 1 Sum of propagation delay time for BC32 2 AC74 and AC04 max 30 5 ns E 1 CS2 1Q AC74 RDY 2...

Страница 380: ...ilable only for areas accessed by CS2 Sum of propagation delay time for BC32 2 AC74 and AC04 max 30 5 ns E L level stop by Ready function Use the elements of which sum of propagation delay time is wit...

Страница 381: ...ch a case generate the __ _ memory read signal OE with delay only the leading edge of the fall of the E Refer to Figure 17 1 12 Fig 17 1 12 Example of causing to delay data output timing Note Satisfy...

Страница 382: ...w are guaranteed However the read signal must go _ high within 10 ns after rising of E signal Table 17 1 5 Memory chips that can be connected without bus buffer tDF tdis OE Maximum 15 ns when guarante...

Страница 383: ...C32 AC04 RD WO WE AC32 XIN XOUT Circuit condition 3 access in low speed running F245 2 2 3 A16 D0 A23 D7 1 CNVSS 4 OC OC Data bus even 1 Use the elements of which propagation delay time is within 20 n...

Страница 384: ...ing 1 A8 D8 A15 D15 A16 D0 A23 D7 E OC F245 RD 5 max 135 min 18 min BC32 tPHL BC32 tPLH D A When reading F245 tPHZ tPLZ F245 tPZH tPZL A8 D8 A15 D15 A16 D0 A23 D7 E 135 min BC32 tPLH D A When writing...

Страница 385: ...Address bus DIR A B A0 R W BHE AC32 AC04 RD WE WO 1D1Q 1T 2D 2Q 2T 1 AC74 AC32 AC04 XIN XOUT ALS245A A8 D8 A15 D15 M37751 A16 D0 A23 D7 1 2 CNVSS 2 OC 1 This circuit ensures that the rising of the wr...

Страница 386: ...5 max 225 min 40 5 min AC32 tPHL AC32 tPLH D A ALS245A tPHZ tPLZ E OC ALS245A ALS245A tPZH tPZL Unit ns D A D AC32 2 tPLH ALS245A tPHZ tPLZ A8 D8 A15 D15 A16 D0 A23 D7 WO WE 2Q AC74 1Q AC74 E OC ALS2...

Страница 387: ...C32 AC04 RD WO WE AC32 XIN XOUT Circuit condition 5 access in high speed running F245 2 2 3 A16 D0 A23 D7 1 CNVSS 4 OC OC Data bus even 1 Use the elements of which propagation delay time is within 45...

Страница 388: ...32 tPLH D A A When reading F245 tPHZ tPLZ F245 tPZH tPZL A8 D8 A15 D15 A16 D0 A23 D7 E 125 min BC32 tPLH D A When writing D F245 tPHL tPLH Unit ns F245 tPHZ tPLZ OC F245 WO WE 35 max External memory d...

Страница 389: ...XIN XOUT F245 A8 D8 A15 D15 M37751 A16 D0 A23 D7 1 2 CNVSS 2 OC 1 This circuit ensures that the rising of the write signal occurs 1 5 1 clock earlier to extend the write hold time Circuit condition 5...

Страница 390: ...C32 tPLH A F245 tPHZ tPLZ F245 tPZH tPZL WO WE 2Q AC74 1Q AC74 E 1 Unit ns D A D Write hold time F245 tPHZ tPLZ 35 max F245 tPHL tPLH OC F245 BC32 tPLH BC32 tPHL 125 min AC04 tPLH AC74 tPLH BC32 tPHL...

Страница 391: ...mple minimum model using a 32 Kbyte SRAM in the memory expansion mode at the high speed running Figure 17 1 24 shows the timing chart for this example Fig 17 1 21 Example of SRAM expansion minimum mod...

Страница 392: ...ow speed running D0 D7 External RAM data output A A D S ta AD 135 min 12 min 5 max 18 min ta OE tsu P2D E 30 15 max Kit guaranteed E OE AC32 tPLH AC32 tPHL ta S E OE A0 A14 A D0 D7 S A A WE D 135 min...

Страница 393: ...14 CNVSS WE 088016 SFR area Internal RAM area External RAM area M5M5256CP Memory map 2 000016 008016 AC32 1 A0 A13 D0 D7 1 2 Use the elements of which propagation delay time is within 15 ns FFFF16 400...

Страница 394: ...n ta OE tsu P2D E 30 15 max Kit guaranteed E OE AC32 tPLH AC32 tPHL ta S E OE A0 A14 A D0 D7 S A A W D 125 min tsu D 30 AC32 tPHL AC32 tPLH 35 max 15 min AC32 tPLH AC32 tPHL A0 A14 When reading Unit n...

Страница 395: ...7 1 28 shows the timing chart for this example Fig 17 1 25 Example of ROM expansion maximum model at low speed running A0 A15 M5M27C102K 12 OE A1 A7 AC04 25 MHz XIN XOUT M37751 BYTE Data bus A1 A16 Ad...

Страница 396: ...xpansion example maximum model at low speed running A8 D8 A15 D15 A16 D0 A 135 min 12 min ta AD AC573 tPHL tPLH CE ta OE R W 20 min ta CE AC04 tPHL 18 min A 5 max D Kit guaranteed tsu P1D P2D E 30 18...

Страница 397: ...D15 A8 A15 000016 008016 SFR area Internal RAM area External ROM area M5M27C102K Memory map Q LE D CNVSS 2 1 AC573 Q LE D A16 1FFFF16 088016 Circuit condition 5 access in high speed running 1 Use the...

Страница 398: ...shows the timing chart for this example 000016 008016 External ROM area M5M27C256AK 2 SFR area Internal RAM area External RAM area M5M5256CP 2 Memory map AC32 AC04 21 MHz XIN XOUT M37751 BYTE A16 A8 A...

Страница 399: ...D0 D1 D7 S A D 165 4 min 35 max 19 6 min AC32 tPHL tsu D 30 Unit ns WE WO AC573 tPHL AC04 tPHL AC32 tPLH A8 D8 A15 D15 A16 D0 External memory data output A D When reading E 165 4 min 19 6 min 5 max 25...

Страница 400: ...D0 D7 M5M27C256AK 12 A1 A15 D0 D7 OE A0 A14 CE A1 A15 S S A0 A14 A0 A14 DQ1 DQ8 DQ1 DQ8 OE W OE W A1 A15 A1 A15 D0 D7 M5M5256CP 70LL OE D8 D15 CE WE A1 A7 A8 D8 A15 D15 ALE A16 D0 D1 D7 R W E A0 BHE C...

Страница 401: ...ta AD ta CE A ta OE AC573 tPHL CE S A A D 104 min 61 7 min AC32 tPHL tsu D 30 AC04 tPHL tsu P0A P1A P2A P1D P2D 150 tsu P1D P2D E 30 BC32 tPHL A 22 2 min BC32 tPLH A A A AC32 tPLH ta S D AC573 tPHL AC...

Страница 402: ...example is described below In this example 8 bit data transmission reception is performed 3 times by using UART0 and 24 bit port expansion is realized Setting of UART0 is described below Clock synchr...

Страница 403: ...clock synchronous serial I O mode Internal clock selected Frequency of transfer clock 1 66 MHz 40 MHz TxD0 RxD0 CLK0 P44 P45 RTS0 M37751 XIN XOUT DI DO CLK CS S VCC GND CNVSS BYTE M66010FP D1 D2 D3 D...

Страница 404: ...anded I O port DO24 DO2 DO1 D1 D2 D24 P4 5 P4 4 CLK 0 T X D 0 R X D 0 Expanded I O port Expanded I O port Terminating floating of expanded I O ports Inputting data of expanded I O ports to shift regis...

Страница 405: ...APPLICATIONS 7751 Group User s Manual 17 40 17 1 Memory expansion MEMORANDUM...

Страница 406: ...CHAPTER 18 PROM VERSION 18 1 EPROM mode 18 2 Usage precaution...

Страница 407: ...version Programming to the PROM can be performed repeatedly because a program can be erased by exposing the erase window on the top of the package to an ultraviolet light source This version can be u...

Страница 408: ...Data input output D0 D7 Input port P3 Input port P4 Control input Input port P5 Input port P6 Input port P7 Input port P8 Pin VCC VSS CNVSS BYTE ______ RESET XIN XOUT _ E AVCC AVSS VREF P00 P07 P10 P...

Страница 409: ...arefully Perform the programming to addresses 1400016 to 1FFFF16 Table 18 1 3 lists the pin correspondence with M5M27C101K Figure 18 1 1 shows the pin connections in EPROM mode Table 18 1 4 lists the...

Страница 410: ...D8 51 P11 A9 D9 50 P12 A10 D10 49 P13 A11 D11 48 P14 A12 D12 47 P15 A13 D13 46 P16 A14 D14 45 P17 A15 D15 44 P20 A16 D0 43 P21 A17 D1 42 P22 A18 D2 41 P23 A19 D3 80 P7 1 AN 1 79 P7 2 AN 2 78 P7 3 AN 3...

Страница 411: ...ly from data I O pins ___ ___ When CE and OE pins are set to H level data I O pins enter the floating state 2 Program Write ___ ___ When CE pin is set to L level and OE pin is set to H level and VPP l...

Страница 412: ...consists of applying a programming pulse of 0 2 ms and read check until the data can be read Additionally record the number of applied pulses before the data has been read Apply pulse 0 2 ms described...

Страница 413: ...e VERIFY ALL BYTE START ADDR FIRST LOCATION 0 VCC VPP 5 0 V DEVICE FAILED DEVICE PASSED VCC 6 0 V VPP 12 5 V 1 25 INCREMENT ADDR VERIFY BYTE DEVICE FAILED LAST ADDR FAIL YES NO PASS PASS YES FAIL PASS...

Страница 414: ...up time ____ PGM pulse width ____ Additional PGM pulse width ___ CE setup time ___ Data delay time after OE tAS tOES tDS tAH tDH tDFP tVCS tVPS tPW tOPW tCES tOE Symbol 2 2 2 0 2 0 2 2 0 19 0 19 2 18...

Страница 415: ...ng of CNVSS VPP pin In single chip or memory expansion mode Connect CNVSS VPP pin to the microcomputer s VSS pin in the shortest possible distance If the wiring cannot be shortened insert a resistor o...

Страница 416: ...te Never expose to 150 C exceeding 100 hours Programming with PROM programmer Fig 18 2 2 Programming and test flow for One Time PROM version 18 2 3 Precautions on EPROM version Cover the transparent g...

Страница 417: ...7751 Group User s Manual PROM VERSION 18 12 18 2 Usage precaution MEMORANDUM...

Страница 418: ...CHAPTER 19 FLASH MEMORY VERSION 19 1 Parallel input output mode 19 2 Serial input output mode...

Страница 419: ...enables to access to the built in flash memory When ______ inputting L level to the RESET pin the M37751F6CFP enters the flash memory mode In the flash memory mode there are two modes the parallel in...

Страница 420: ...memory can be accessed by using a general purpose ROM programmer in the parallel I O mode In this mode the read only mode or the read write mode software command control mode can be selected as the bu...

Страница 421: ...ead only mode Supply Vcc to Vcc 1 0 V Read write mode Supply 12 V 5 Connect to Vss pin Connect to Vss pin Connect a ceramic resonator or quartz crystal oscillator between XIN and XOUT pins When using...

Страница 422: ...s not contain a facility to read out a device identification code by applying a high voltage to A9 P11 pin Do not erratically set program conditions etc Table 19 1 2 lists the pin correspondence of th...

Страница 423: ...6 20 P4 5 21 P4 4 22 P4 3 23 P4 2 1 24 56 P0 4 A 4 55 P0 5 A 5 54 P0 6 A 6 53 P0 7 A 7 52 P1 0 A 8 D 8 51 P1 1 A 9 D 9 50 P1 2 A 10 D 10 49 P1 3 A 11 D 11 48 P1 4 A 12 D 12 47 P1 5 A 13 D 13 46 P1 6...

Страница 424: ...e 19 1 3 lists the states of the built in flash memory Table 19 1 3 States of control signals and built in flash memory in read only mode ___ CE VIL VIL VIH ___ OE ___ WE VPP VPPL VPPL VPPL Pin State...

Страница 425: ...N 7751 Group User s Manual 19 8 19 1 Parallel input output mode 2 Output disable The microcomputer enters the read disable state 3 Standby The microcomputer enters the power saving state and the suppl...

Страница 426: ...n flash memory Table 19 1 4 States of control signals and built in flash memory in read write mode ___ CE ___ OE ___ WE VPP VPPH VPPH VPPH VPPH Pin State Data I O Read Output disable Standby Program V...

Страница 427: ...le The following explains each software command Table 19 1 5 Software command and input output information Read Program Program verify Erase Erase verify Reset Device identification First cycle Softwa...

Страница 428: ...mand code 0016 in the first cycle The data of the specified address input address is output to an external by inputting the address and control signals in the second cycle The read command code which...

Страница 429: ...ess within 10 s as measured by its internal timer Programming is performed by the byte unit Note Be sure to execute a program verify command after executing the program command If this verification fa...

Страница 430: ...E WE D 0 D 7 t WPH t CS 40 16 t DF t OH Floating Verify data output t RRW t CH t CS t DS t VSC First cycle V PP H V PP L V PP t WP t DH t a OE Data C0 16 Program address Program Data t AS t AH t WP t...

Страница 431: ...te Be sure to execute a erase verify command after executing the erase command If this verification fails execute repeatedly the erase command and the erase verify command until the verification passe...

Страница 432: ...OE WE D 0 D 7 t WPH t CS 20 16 t DF t OH Floating Verify data output t RRW t CH t CS t DS t VSC First cycle V PP H V PP L V PP t WP t DH t a OE A0 16 Erase Data t WP t CH t DS t DH t CS t WP t CH t D...

Страница 433: ...and code is latched into the command latch the command code is latched into the ___ internal command latch at the rising edge of the WE signal When inputting the control signals and command code FF16...

Страница 434: ...xternally when inputting an address 0000016 and the control signals in the second cycle The device code D016 i e 1M bit flash memory is output externally when inputting an address 0000116 and the cont...

Страница 435: ...Vcc 0 2 V Vcc 5 5 V CE VIL tRC 150 ns Iout 0 mA VPP VPPH VPP VPPH 0 VPP Vcc 1 0 V VPP VPPH VPP VPPH VPP VPPH 12 0 Vcc 11 4 Note VIH VIL VOH VOL and IIH IIL for the control input address input and data...

Страница 436: ...ress setup time Address hold time Data setup time Data hold time Write recovery time before read Read recovery time before write ___ CE setup time ___ CE hold time Write pulse time Write pulse waiting...

Страница 437: ...SS LAST ADDR NO PASS WRITE READ COMMAND YES VPP VPPL DEVICE PASSED DEVICE FAILED INCREMENT ADDR Program VCC 5V VPP VPPH ADDR FIRST LOCATION X 0 WRITE PROGRAM WRITE PROGRAM DATA DURATION 10 s X X 1 WRI...

Страница 438: ...t output mode 19 2 Serial input output mode In the serial I O mode the contents of the built in flash memory can be reprogrammed with the state mounting the microcomputer on the board 19 2 1 Pin descr...

Страница 439: ...k the clock source must be input to XIN pin and XOUT pin must be left open H level is output Connect to Vcc pin Connect to Vss pin Input level between Vss and Vcc or open Input H or L level or open In...

Страница 440: ...rial I O mode the built in flash memory is accessed by inputting execution of the software command Table 19 2 2 lists the software command To execute the software command requires twice or four times...

Страница 441: ...IN 17 P5 0 TA0 OUT 18 P4 7 19 P4 6 20 P4 5 21 P4 4 22 P4 3 23 P4 2 1 24 56 P0 4 A 4 55 P0 5 A 5 54 P0 6 A 6 53 P0 7 A 7 52 P1 0 A 8 D 8 51 P1 1 A 9 D 9 50 P1 2 A 10 D 10 49 P1 3 A 11 D 11 48 P1 4 A 1...

Страница 442: ...ata latch ___ When returning H level to the OE signal and inputting the serial clock the data which is latched up to the data latch is output externally Note When outputting the read data the SDA pin...

Страница 443: ...The input data is programmed to the specified address input address within 10 s as measured by the built in timer and the BUSY signal becomes L level Programming is performed by the byte unit Note Be...

Страница 444: ...___ When returning the OE signal to H level and inputting the serial clock the data which is latched to the data latch is output externally Since the address is internally latched when the program com...

Страница 445: ...signal becomes H level The BUSY signal becomes L by erasing all the contents of the built in flash memory Note When executing the auto erase command once erase erase verify is performed repeatedly int...

Страница 446: ...level again to select the serial I O mode and initialize the serial communication circuit The error information is output when first executing the error check command after initializing Figure 19 2 7...

Страница 447: ...ive command codes shown in Table 19 2 2 this flag becomes 1 Address error flag E1 When inputting the addresses other than addresses 400016 to FFFF16 this flag becomes 1 The contents are undefined at r...

Страница 448: ...transmission interval time Read waiting time after transmission Read pulse width Transfer waiting time after read Waiting time before program verify Programming time Transfer waiting time after progr...

Страница 449: ...al 19 32 19 2 Serial input output mode Timing tC CK tW CKL tW CKH tf CK tr CK td C Q th C E th C Q th C D tsu D C Test conditions Output timing voltage VOL 0 8 V VOH 2 0 V Input timing voltage VIL 0 2...

Страница 450: ...T VCC 5 V SDA SCLK OE H VPP VPPH ADDR FIRST LOCATION X 0 WRITE PROGRAM COMMAND WRITE PROGRAM DATA DURATION 10 s X X 1 WRITE PROGRAM VERIFY COMMAND DURATION 6 X 25 VERIFY BYTE VERIFY BYTE LAST ADDR NO...

Страница 451: ...FLASH MEMORY VERSION 7751 Group User s Manual 19 34 19 2 Serial input output mode MEMORANDUM...

Страница 452: ...n SFR area Appendix 3 Control registers Appendix 4 Package outlines Appendix 5 Example for processing unused pins Appendix 6 Hexadecimal instruction code table Appendix 7 Machine instructions Appendix...

Страница 453: ...dix 1 Memory assignment 1 During single chip mode 00000016 00008016 00400016 00FFFF16 00087F16 M37751M6C XXXFP M37751E6C XXXFP M37751E6CFS M37751F6CFP Type name SFR area Internal RAM 2048 bytes Not us...

Страница 454: ...emory expansion mode 00000016 00008016 00400016 00FFFF16 00087F16 SFR area External area Internal ROM area 48 Kbytes Internal RAM area 2048 bytes External area Bank 116 Bank FF16 Bank 016 01000016 01F...

Страница 455: ...000016 00008016 00FFFF16 00087F16 SFR area Internal RAM area 2048 bytes External area Bank 116 Bank FF16 Bank 016 01000016 01FFFF16 FF000016 FFFFFF16 00000216 SFR area External area 00000916 M37751M6C...

Страница 456: ...The written value becomes valid data It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value is ignored RW RO WO Access characteristics 0 i...

Страница 457: ...state Nothing is assigned It is impossible to read the bit state The written value is ignored RW RO WO Access characteristics 0 immediately after a reset 1 immediately after a reset Undefined immedia...

Страница 458: ...t reading 0 immediately after a reset Fix this bit to 0 State immediately after a reset Register name Address Access characteristics State immediately after a reset Timer B2 register Timer A2 register...

Страница 459: ...l register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Timer B0 inte...

Страница 460: ...de or state It may be either 0 or 1 Nothing is assigned 2 0 0 immediately after a reset 1 1 immediately after a reset Undefined Undefined immediately after a reset 3 RW It is possible to read the bit...

Страница 461: ...d Undefined Undefined Undefined Undefined Undefined Undefined 0 L level 1 H level RW RW RW RW RW RW RW RW Port Pi direction register Bit Bit name Functions 0 1 2 3 4 5 6 7 Port Pi0 direction bit Port...

Страница 462: ...ersion 1 Start A D conversion b4 b3 Notes 1 These bits are ignored in the single sweep repeat sweep mode 0 and repeat sweep mode 1 They may be either 0 or 1 2 When selecting an external trigger the AN...

Страница 463: ...al trigger the AN7 pin cannot be used as an analog input pin 3 Analog input pins which are frequently A D converted are selected in the repeat sweep mode 1 4 Fix this bit to 0 in the one shot repeat a...

Страница 464: ...t 7 to 0 At reset 0 Undefined RW Functions RO b7 b0 b15 b8 Reads an A D conversion result 15 to 8 The value is 0 at reading 8 bit mode b7 b0 A D register 0 Addresses 2116 2016 A D register 1 Addresses...

Страница 465: ...bit Valid in UART mode Note Odd Even parity select bit Valid in UART mode when parity enable bit is 1 Note Stop bit length select bit Valid in UART mode Note Internal External clock select bit UART0 t...

Страница 466: ...b5 b4 b3 b2 b1 b0 0 0 f2 f4 0 1 f16 f32 1 0 f64 f128 1 1 f512 f1024 UART0 transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 b1 b0 0 CTS function...

Страница 467: ...in the clock synchronous serial I O mode 0 Transmit enable bit 0 0 Transmission disabled 1 Transmission enabled 1 Transmit buffer empty flag 1 0 Data present in transmit buffer register 1 No data pre...

Страница 468: ...RW Functions b7 b6 b5 b4 b3 b2 b1 b0 Count start register Address 4016 0 Stop counting 1 Start counting RW RW RW RW RW RW RW RW 0 1 2 3 4 5 6 7 Bit 7 to 5 Nothing is assigned Timer A4 one shot start...

Страница 469: ...A3 two phase pulse signal processing select bit Note Timer A4 two phase pulse signal processing select bit Note 0 Down count 1 Up count This function is valid when the contents of the up down register...

Страница 470: ...dresses 4F16 4E16 Functions Bit At reset RW 15 to 0 These bits have different functions according to the operating mode Undefined RW Bit 7 5 4 3 1 Bit name At reset 0 0 0 0 0 0 0 0 RW Functions b7 b6...

Страница 471: ...tion select bits Pulse output function select bit 1 Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 0 0 Timer mode 0 No pul...

Страница 472: ...1 0 No pulse output TAiOUT pin functions as a programmable I O port 1 Pulse output TAiOUT pin functions as a pulse output pin 0 1 Event counter mode b1 b0 0 0 0 0 2 RW RW 3 4 5 6 RW RW RW RW RW RW Ti...

Страница 473: ...cy of count source f2 f4 f16 f32 f64 f128 or f512 f1024 WO Trigger select bits Fix this bit to 1 in one shot pulse mode 1 Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Ai mode register i 0 to 4 Add...

Страница 474: ...E16 Functions Bit At reset RW 7 to 0 15 to 8 Undefined Undefined These bits can be set to 0016 to FF16 Assuming that the set value m PWM pulse s period output from the TAiOUT pin is expressed as follo...

Страница 475: ...g is assigned These bits have different functions according to the operating mode 1 Operating mode select bits Bit name Functions b7 b6 b5 b4 b3 b2 b1 b0 Timer Bi mode register i 0 to 2 Addresses 5B16...

Страница 476: ...0 2 RW RW 3 RW RW Timer Bi mode register i 0 to 2 Addresses 5B16 to 5D16 0 0 0 Undefined 4 Undefined 5 6 7 0 0 f2 f4 0 1 f16 f32 1 0 f64 f128 1 1 f512 f1024 b7 b6 RW 0 RW 0 b7 b0 b7 b0 b15 b8 Timer B...

Страница 477: ...indicates the counter value Undefined 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 1 0 Counts at both falling and rising edges of external signal 1 1 Not se...

Страница 478: ...between rising edges of measurement pulse 1 0 Pulse width measurement Interval from a falling edge to a rising edge and from a rising edge to a falling edge of measurement pulse 1 1 Not selected Bit A...

Страница 479: ...uter is reset by writing 1 to this bit The value is 0 at reading 0 0 7 cycles of 0 1 4 cycles of 1 0 2 cycles of 1 1 Not selected 0 Clock 1 output disabled P42 functions as a programmable I O port 1 C...

Страница 480: ...s in high speed running 1 0 3 access in high speed running 1 1 Not selected Note Fix this bit to 0 when f XIN 25 MHz Fix these bits to 0 4 7 6 RW RW RW RW 0 0 0 Clock source for peripheral devices sel...

Страница 481: ...ten to this register the watchdog timer s value is initialized to FFF16 Dummy data 0016 to FF16 At reset Undefined RW Functions 7 to 0 Watchdog timer frequency select register 0 Wf512 Wf1024 1 Wf32 Wf...

Страница 482: ...bit becomes undefined after reset Note b7 b6 b5 b4 b3 b2 b1 b0 INT0 to INT2 interrupt control registers Addresses 7D16 to 7F16 Bit 4 Interrupt request bit Note 2 1 0 Bit name At reset 0 RW Functions...

Страница 483: ...APPENDIX 7751 Group User s Manual 20 32 Appendix 4 Package outlines Appendix 4 Package outlines 80P6N A...

Страница 484: ...APPENDIX 7751 Group User s Manual 20 33 Appendix 4 Package outlines 80D0...

Страница 485: ...hen setting these ports to the output mode and leave them open they remain set to the input mode until they are switched to the output mode by software after reset While ports remain set to the input...

Страница 486: ...ut mode consequently voltage levels of pins are unstable and a power source current can increase The contents of the direction register can be changed by noise or a program runaway generated by noise...

Страница 487: ...In single chip mode P0 P8 AVSS VREF BYTE M37751 VSS AVCC E XOUT P42 P47 P5 P8 1 AVSS VREF HOLD RDY M37751 VSS AVCC In memory expansion mode and microprocessor mode XOUT ALE VCC VCC When setting ports...

Страница 488: ...APPENDIX 7751 Group User s Manual 20 37 Appendix 6 Hexadecimal instruction code table Appendix 6 Hexadecimal instruction code table...

Страница 489: ...APPENDIX 7751 Group User s Manual 20 38 Appendix 6 Hexadecimal instruction code table...

Страница 490: ...APPENDIX 7751 Group User s Manual 20 39 Appendix 6 Hexadecimal instruction code table...

Страница 491: ...APPENDIX 7751 Group User s Manual 20 40 Appendix 7 Machine instructions Appendix 7 Machine instructions...

Страница 492: ...APPENDIX 7751 Group User s Manual 20 41 Appendix 7 Machine instructions...

Страница 493: ...APPENDIX 7751 Group User s Manual 20 42 Appendix 7 Machine instructions...

Страница 494: ...APPENDIX 7751 Group User s Manual 20 43 Appendix 7 Machine instructions...

Страница 495: ...APPENDIX 7751 Group User s Manual 20 44 Appendix 7 Machine instructions...

Страница 496: ...APPENDIX 7751 Group User s Manual 20 45 Appendix 7 Machine instructions...

Страница 497: ...APPENDIX 7751 Group User s Manual 20 46 Appendix 7 Machine instructions...

Страница 498: ...APPENDIX 7751 Group User s Manual 20 47 Appendix 7 Machine instructions...

Страница 499: ...APPENDIX 7751 Group User s Manual 20 48 Appendix 7 Machine instructions...

Страница 500: ...APPENDIX 7751 Group User s Manual 20 49 Appendix 7 Machine instructions...

Страница 501: ...APPENDIX 7751 Group User s Manual 20 50 Appendix 7 Machine instructions...

Страница 502: ...APPENDIX 7751 Group User s Manual 20 51 Appendix 7 Machine instructions...

Страница 503: ...APPENDIX 7751 Group User s Manual 20 52 Appendix 7 Machine instructions...

Страница 504: ...APPENDIX 7751 Group User s Manual 20 53 Appendix 7 Machine instructions...

Страница 505: ...APPENDIX 7751 Group User s Manual 20 54 Appendix 7 Machine instructions...

Страница 506: ...APPENDIX 7751 Group User s Manual 20 55 Appendix 7 Machine instructions...

Страница 507: ...APPENDIX 7751 Group User s Manual 20 56 Appendix 7 Machine instructions...

Страница 508: ...APPENDIX 7751 Group User s Manual 20 57 Appendix 7 Machine instructions...

Страница 509: ...APPENDIX 7751 Group User s Manual 20 58 Appendix 7 Machine instructions...

Страница 510: ...APPENDIX 7751 Group User s Manual 20 59 Appendix 7 Machine instructions...

Страница 511: ...APPENDIX 7751 Group User s Manual 20 60 Appendix 7 Machine instructions...

Страница 512: ...omputer The shorter the total wiring length by mm unit the less possibility of noise insertion into the microcomputer 1 ______ Wiring for RESET pin ______ Make the length of wiring connected to RESET...

Страница 513: ...This may cause a malfunction or a program runaway Also if the noise causes a potential difference between the Vss level of the microcomputer and the Vss level of an oscillator the correct clock will...

Страница 514: ...in with the shortest possible wiring Reason CNVss VPP pin is connected to the internal ROM in the low impedance state Noise is easily fed to the pin in this condition If noise enters the CNVss VPP pin...

Страница 515: ...lows Connect a bypass capacitor between the Vss and Vcc pins at equal lengths The wiring connecting the bypass capacitor between the Vss and Vcc pins should be as short as possible Use thicker wiring...

Страница 516: ...hich measures changes in status tends to be installed far from the microcomputer printed circuit board The result is long wiring that becomes an antenna which picks up noise and feeds it into the micr...

Страница 517: ...r Vcc AVcc and VREF pins Insert capacitors between the AVcc and AVss pins and between the VREF and AVss pins Reasons Prevents the A D converter from noise on the Vcc line Fig 11 Processing analog powe...

Страница 518: ...unaway 4 Oscillator protection The oscillator which generates the basic clock for the microcomputer operations must be protected from the affect of other signals 1 Distance oscillator from signal line...

Страница 519: ...board under the oscillator mount position Connect the Vss pattern to Vss pin of the microcomputer with the shortest possible wiring separating it from other Vss patterns Fig 14 Vss pattern underneath...

Страница 520: ...ohms or more to an I O port in series Software protection As for an input port read data several times for checking whether input levels are equal or not As for an output port since the output data ma...

Страница 521: ...de the microcomputer is installed at the center and the Vss line is looped or meshed around it The vacant area is filled with the Vss line On the opposite side the Vcc line is wired the same as the Vs...

Страница 522: ...a rule one question and its answer are summarized within one page The upper box on each page is a question and a box below the question is its answer If a question or an answer extends to two or more...

Страница 523: ...th the CPU s op code fetch cycles 1 If the next interrupt request b occurs before the sampling pulse for the RTI instruction is generated the microcomputer executes the INTACK sequence for b without e...

Страница 524: ...sses the address and data to the BIU Then the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address Detection of interrupt priority le...

Страница 525: ...ng shows a sample program Sample program After an instruction which writes 0002 to the interrupt priority level select bits fill the instruc tion queue buffer with the NOP instruction to make the next...

Страница 526: ...c to the INTi pin and input each signal to each corresponding port ___ In software check the port s input levels in the INTi interrupt routine to determine that which of the signals a b and c is input...

Страница 527: ...____ transmitting side check the CTS input level It is check near the middle of the stop bit when two stop bits are selected the second stop bit A Q Serial I O UART mode D6 n 1 bit length D7 SP SP n n...

Страница 528: ...input to the HOLD pin how long is the bus actually opened A The bus is opened after 50 ns at maximum has passed from the rising edge of next clock 1 when ____ the HLDA pin output becomes L level Q Hol...

Страница 529: ...ction queue buffer can prefetch up to three instructions the address in the external ROM area and is accessed first after the mode is switched is one of XXXX16 1 to XXXX16 4 The instructions at addres...

Страница 530: ...structions i e CLB SEB INC DEC ASL ASR LSR ROL and ROR UART0 baud rate register address 3116 UART1 baud rate register address 3916 UART0 transmit buffer register addresses 3316 3216 UART1 transmit buf...

Страница 531: ...processor mode register 1 address 5F16 to the following The microcomputer becomes the following state by the setting above f4 f32 f128 or f1024 can be selected for the operating clock of internal peri...

Страница 532: ...o set this bit to 1 However do not set bits 5 to 3 at address 5F16 to 0012 When setting bit 3 at address 5F16 to 1 set bit 5 bit 4 or both bits 5 and 4 to 1 at the same time because bits 5 and 4 at ad...

Страница 533: ...16 and the processor mode register 1 address 5F16 The A D conversion interrupt request bit bit 3 at address 7016 is undefined at reset Set this bit to 0 by software before use Clear the receive enable...

Страница 534: ...The CPU registers and the SFR are not initialized in the above mentioned way Accordingly the user must perform the initial setting for these all by software The processor interrupt priority level IPL...

Страница 535: ...APPENDIX Appendix 9 Q A 7751 Group User s Manual 20 84 MEMORANDUM...

Страница 536: ...GLOSSARY...

Страница 537: ...f this routine into the interrupt vector address Means a transfer data format of Serial I O LSB is transferred first Means a transfer data format of Serial I O MSB is transferred first A state where t...

Страница 538: ...increasing by 1 and counting A state where the oscillation circuit is operating however the program execution is stopped By executing the WIT instruction the microcomputer enters Wait mode Relevant t...

Страница 539: ...GLOSSARY 7751 Group User s Manual 4 MEMORANDUM...

Страница 540: ...Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form with...

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