Reliance electric 57C409, Инструкция по эксплуатации

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4Ć3
Registers 7 and 8 contain the update period for the analog to digital
conversion. Each count in these registers is equivalent to 500
microseconds. The update period may range from 500 microseconds
to 32.7675 seconds. These two registers must be initialized before
the common clock is enabled on the backplane. Refer to figure 4.5.
Refer to figure 4.4 for more information about the common clock.
register 7
register 8
update period for channel 0
update period for channel 1
bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 4.5 Ć Analog Update Registers
Registers 9 and 10 contain the input filter being used. The purpose of
the filter is to remove signal components that are beyond the
samplingfrequency. Note that the module requires a short delay
between statements used to initialize these two registers. The
minimum delay time between initialization of the two registers is 5.5
msec. The input filter registers must be initialized after the common
clock is turned on. Refer to figure 4.6 for the cutoff frequencies
available.
register 10
channel 1
00 = 300 rad/sec
01 = 145 rad/sec
10 = ă79 rad/sec
11 = ă21 rad/sec
rw rw
register 9
channel 0
- - - - - - -
- - - - - - -
- - -
- - -
rw rw - - - -
- - - -
+ Input filter
bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 4.6 Ć Input Filter Selection Registers