Direct Memory Access Controller (DMAC)
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101
Fig 9-14 Hardware handshaking interface
Table 9-3 describes the operation of the hardware handshaking interface signals when the peripheral is the flow controller; timing diagrams
are illustrated in Fig 9-15 and Fig 9-16
Table 9-3 Hardware handshaking interface
Signal
Direction
Description
dma_ack
Output
DMAC acknowledge signal to the peripheral. This is asserted after the data phase of the last AHB transfer in
the current transaction (single or burst) to the peripheral has completed. It forms a handshaking loop with
dma_req and remains asserted until the peripheral de-asserts dma_req (de-asserted one hclk cycle later).
dma_finish
Output
DMAC block transfer complete signal. The DMAC asserts dma_finish in order to signal block completion. This
uses the same timing as dma_ack and forms a handshaking loop with dma_req.
dma_last
Input
Last transaction in block. When the peripheral is the flow controller, it asserts dma_last on the same cycle as
dma_req is asserted in order to signal that this transaction request is the last in the block; the block transfer is
complete after this transaction is complete. If dma_single is high in the same cycle, then the last transaction is
a single transaction. If dma_single is low in the same cycle, then the last transaction is a burst transaction.
dma_req
Input
Transaction request from peripheral. An active level on dma_req initiates a transaction request. The type of
transaction – single or burst – is qualified by dma_single. Once dma_req is asserted, it must remain asserted
until dma_ack is asserted. When the peripheral that is driving dma_req determines that dma_ack is asserted, it
must de-assert dma_req.
dma_single
Input
Single or burst transaction request. If dma_single is de-asserted in the same clock cycle as a rising edge on
dma_req, a burst transaction is requested by the peripheral. If asserted, the peripheral requests a single
transaction.
The following timing diagrams assume that handshaking interface 0 is active-high.
Fig 9-15 shows a burst transaction followed by a single transaction, where the single transaction is the last in the block. On clock edge T1,
DMAC samples that dma_req[0] is asserted, dma_single[0] is de-asserted, and dma_last[0] is de-asserted. This is a request for a burst
transaction, which is not the last transaction in the block.
Fig 9-15 Burst transaction followed by single transaction that terminates block
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