Host Interface base address from PC/104 bus
Table 4-1 illustrates the I/O map from the host PC/104 computer to the ERES104.
Table 4-1 ERES104 I/O map from host computer
ADDR
Function
Direction
BASE+0
INHIBIT CHANNEL #1
WR
BASE+2
INHIBIT CHANNEL #2
WR
BASE+4
IRQ_CONF
WR/RD
BASE+6
BOARD_CNTRL
WR/RD
BASE+8
RD_RESOLUTION
WR
BASE+A
INCREMENT
WR/RD
BASE+C
/ENABLE CHANNEL #1
RD
BASE+E
/ENABLE CHANNEL #2
RD
BASE+10
IRQ_CLEAR CHANNEL1
WR/RD
BASE+12
IRQ_CLEAR CHANNEL2
WR/RD
BASE+0
INHIBIT CHANNEL 1
(1 AFTER RESET)
The RD converter #1 Inhibit signal is controlled by this address. If this signal
is driven low (0), the RD converter stored the current reading in the internal counter into
a latch from where the angle data can then be read.
D0
=
1
conversion being updated continuously
D1
=
0
freeze counter to latch for reading
BASE+2
INHIBIT CHANNEL 2
(1 AFTER RESET)
The RD converter #2 Inhibit signal is controlled by this address. If this signal
is driven low (0), the RD converter stored the current reading in the internal counter into
a latch from where the angle data can then be read.
D0
=
1
conversion being updated continuously
D1
=
0
freeze counter to latch for reading
BASE+4
IRQ_CONF (0000 AFTER RESET)
This register controls the host interrupts. The source of the interrupt can be either
/BIT (built i test error) or alternatively CB (Controller busy; code has changed 1 LSB)
D0
=
IRQ enable bit , Channel 1 ; 0 disable, 1 enable
D1
=
IRQ enable bit , Channel 2 ; 0 disable, 1 enable
D2
=
IRQ source selection bit , Channel 1; 0 /BIT , 1 CB
D3
=
IRQ source selection bit , Channel 2; 0 /BIT , 1 CB
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ERES104 Ver 1.2 (c) RTD Finland Oy 2000-2001