Rx-URME-007 Rev - -2
- Preliminary -
PMC665 Hardware Reference and Installation Manual
Page 7
registers, load/store memory access, etc. In addition, the i960 features a “register stack”
mechanism that maintains initial interrupt response on chip, which improves performance and
determinism.
The co-processor can initiate all transaction types on each of the three buses.
Included in the bridge/co-processor are the DMA engines (described earlier), several counter/
timers to support time based event activity of the firmware and an interrupt multiplexer/handler for
responding to the Ethernet controllers. Both register and message based interfaces to the host
processor are available, allowing support of a variety of control paradigms. This greatly simplifies
integrating the PMC665 into some existing software environments, while preserving the ability to
develop higher performance complex message based controls.
Integrating the processor and bridge has the useful side effect of exposing most of the control
logic to the host processor (mapped into the PCI Configuration space and optionally the memory
space of the host). This creates the option for a continuum of control distribution, between the
host and co-processor. The PMC665 can be configured such that the:
•
bridge/co-processor functions primarily as a bridge, with control local to the host
•
with one Ethernet under control of the host, the other by the co-processor or
•
with all low level control resident in the co-processor
How the PMC665 responds to PCI configuration requests from the host can be altered by on-
board firmware. Upon power-up (or reset), the on-board processor performs a Built-In-Test (BIT)
sequence of the internal (Bridge/co-processor) operation, local memory subsystem and Ethernet
controllers. Results are available to the host via configuration registers. During the BIT, the co-
processor loads firmware from the FLASH device. It is this firmware that controls how the
PMC665 behaves in relationship to the host and the Ethernet interfaces. The on-board FLASH is
512Kbytes; 128Kbyte is reserved for customer-specific configuration parameters. It is possible to
update the FLASH contents either from the host, or (with appropriate on-board firmware loaded)
over the Ethernet.
The switch is set at the factory for different modes of operations: with processor enabled or
disabled. If enabled, the processor will load firmware from on card flash and begin execution. If
Disabled, the processor will be held in reset. In this condition the PCI bridge functions remain
operational, the PMC665 can be treated as an unintelligent dual network card.
3.0.4
Ethernet Controllers
The Ethernet Controllers on the PMC665 have enjoyed several years of active evolution, featuring
improvements at both the PCI bus and Ethernet interface. Each controller is a fully independent
unit, with local FIFO buffers to decouple PCI and Ethernet activity. Decoupling the Ethernet and
PCI ensures that data transfers will meet the timing requirements of each transaction (which is of
particular importance on the Ethernet) regardless of the loading on the other bus interface. These
FIFO buffers are sufficiently deep to support good burst transfers and presenting minimum
overhead to the PCI bus. When doing data transfer on the PCI bus the Ethernet DMA engine will
attempt to maximize the length of burst transactions, which is critical to obtain the potential
bandwidth of the PCI protocol. These properties allow sustained full bandwidth transfers on both
Ethernet ports.
3.0.5
Fiber Connections
The PMC665 uses two Dual Transceivers with SC style connectors, and PMC665A uses the ST
style connectors. The Transceivers are fully compliant with the standards defined by the Feast
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