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Instruction Reference Manual
143
Description
Logically shifts to the right the bits in r (any of the registers A, B, C, D, E, H, or L). Each bit is shifted to the
next lowest-order bit position (Bit 7 shifts to bit 6, etc.) Bit 0 shift to the C flag. Bit 7 is reset. See Figure 9 on
page 142.
SRL
r
Opcode
Instruction
Clocks
Operation
——
CB 3F
CB 38
CB 39
CB 3A
CB 3B
CB 3C
CB 3D
SRL
r
SRL A
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
4 (2,2)
r
= {0,
r
[7,1]}; CF =
r
[0]
A = {0,A[7,1]}; CF = A[0]
B = {0,B[7,1]}; CF = B[0]
C = {0,C[7,1]}; CF = C[0]
D = {0,D[7,1]}; CF = D[0]
E = {0,E[7,1]}; CF = E[0]
H = {0,H[7,1]}; CF = H[0]
L = {0,L[7,1]}; CF = L[0]
Flags
ALTD
I/O
S
Z
L/V
C
F
R
SP
S
D
•
•
L
•
•
•
Содержание 2000
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